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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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module THEIA
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module THEIA
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(
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(
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//Theia Interfaces
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//Theia Interfaces
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input wire MST_I, //Master signal, THEIA enters configuration mode
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input wire MST_I, //Master signal, THEIA enters configuration mode
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//when this gets asserted (see documentation)
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//when this gets asserted (see documentation)
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//Wish Bone Interface
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//Wish Bone Interface
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input wire [`WB_WIDTH-1:0] DAT_I, //Input data bus (Wishbone)
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input wire [`WB_WIDTH-1:0] DAT_I, //Input data bus (Wishbone)
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//output wire [`WB_WIDTH-1:0] DAT_O, //Output data bus (Wishbone)
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input wire ACK_I, //Input ack
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input wire ACK_I, //Input ack
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output wire ACK_O, //Output ack
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output wire ACK_O, //Output ack
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//output wire [`WB_WIDTH-1:0] ADR_O, //Output address
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input wire [`WB_WIDTH-1:0] ADR_I, //Input address
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input wire [`WB_WIDTH-1:0] ADR_I, //Input address
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//output wire WE_O, //Output write enable
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input wire WE_I, //Input write enable
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input wire WE_I, //Input write enable
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//output wire STB_O, //Strobe signal, see wishbone documentation
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input wire STB_I, //Strobe signal, see wishbone documentation
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input wire STB_I, //Strobe signal, see wishbone documentation
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//output wire CYC_O, //Bus cycle signal, see wishbone documentation
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input wire CYC_I, //Bus cycle signal, see wishbone documentation
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input wire CYC_I, //Bus cycle signal, see wishbone documentation
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//output wire [1:0] TGC_O, //Bus cycle tag, see THEAI documentation
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input wire [1:0] TGA_I, //Input address tag, see THEAI documentation
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input wire [1:0] TGA_I, //Input address tag, see THEAI documentation
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//output wire [1:0] TGA_O, //Output address tag, see THEAI documentation
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//input wire [1:0] TGC_I, //Bus cycle tag, see THEAI documentation
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input wire [`MAX_CORES-1:0] SEL_I, //The WishBone Master uses this signal to configure a specific core (TBD, not sure is needed)
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input wire [`MAX_CORES-1:0] SEL_I, //The WishBone Master uses this signal to configure a specific core (TBD, not sure is needed)
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input wire [`MAX_CORES-1:0] RENDREN_I,
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input wire [`MAX_CORES-1:0] RENDREN_I,
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input wire [`MAX_CORE_BITS-1:0] OMBSEL_I, //Output memory bank select
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input wire [`MAX_CORE_BITS-1:0] OMBSEL_I, //Output memory bank select
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input wire [`WB_WIDTH-1:0] OMADR_I, //Output adress (relative to current bank)
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input wire [`WB_WIDTH-1:0] OMADR_I, //Output adress (relative to current bank)
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wire [`MAX_CORES-1:0] wACK_I;
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wire [`MAX_CORES-1:0] wACK_I;
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wire [`MAX_CORES-1:0] wCYC_I;
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wire [`MAX_CORES-1:0] wCYC_I;
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wire [1:0] wTGA_I[`MAX_CORES-1:0];
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wire [1:0] wTGA_I[`MAX_CORES-1:0];
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//wire [`MAX_CORES-1:0] wTMEM_ACK_I;
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wire [`WB_WIDTH-1:0] wTMEM_Data;
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wire [`WB_WIDTH-1:0] wTMEM_Data;
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wire [`WB_WIDTH-1:0] wTMEM_Address[`MAX_CORES-1:0];
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wire [`WB_WIDTH-1:0] wTMEM_Address[`MAX_CORES-1:0];
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wire [`WB_WIDTH-1:0] wTMEM_ReadAddr;
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wire [`WB_WIDTH-1:0] wTMEM_ReadAddr;
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//wire [`MAX_CORES-1:0] wTMEM_STB_O;
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wire [`MAX_CORES-1:0] wTMEM_Resquest;
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wire [`MAX_CORES-1:0] wTMEM_Resquest;
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wire [`MAX_CORES-1:0] wTMEM_Granted;
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wire [`MAX_CORES-1:0] wTMEM_Granted;
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wire [`MAX_CORES-1:0] wBankReadGranted[`MAX_TMEM_BANKS-1:0];
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wire [`MAX_CORES-1:0] wBankReadGranted[`MAX_TMEM_BANKS-1:0];
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wire wTMEM_2_Core__Grant[`MAX_CORES-1:0];
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wire wTMEM_2_Core__Grant[`MAX_CORES-1:0];
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wire[`MAX_CORE_BITS-1:0] wCurrentCoreSelected[`MAX_TMEM_BANKS-1:0];
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wire[`MAX_CORE_BITS-1:0] wCurrentCoreSelected[`MAX_TMEM_BANKS-1:0];
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//wire [`WB_WIDTH-1:0] wTMEM_2_Core_Data[`MAX_CORES-1:0]; //Vertical grid Buses going to each core.
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wire[`WIDTH-1:0] wCoreBankSelect[`MAX_CORES-1:0];
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wire[7:0] wCoreBankSelect[`MAX_CORES-1:0];
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wire [`MAX_CORES-1:0] wGRDY_O;
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wire [`MAX_CORES-1:0] wGRDY_O;
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wire [`MAX_CORES-1:0] wGReady;
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wire [`MAX_CORES-1:0] wGReady;
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wire [`MAX_CORES-1:0] wRCOMMIT_O;
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wire [`MAX_CORES-1:0] wRCOMMIT_O;
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wire [`MAX_CORES-1:0] wRCommited;
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wire [`MAX_CORES-1:0] wRCommited;
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assign RCOMMIT_O = wRCommited[0] & wRCommited[1] & wRCommited[2] & wRCommited[3];
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assign RCOMMIT_O = wRCommited[0] & wRCommited[1] & wRCommited[2] & wRCommited[3] & wRCommited[4] & wRCommited[5] & wRCommited[6] & wRCommited[7] & wRCommited[8] & wRCommited[9] & wRCommited[10] & wRCommited[11] & wRCommited[12] & wRCommited[13] & wRCommited[14] & wRCommited[15];
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assign GRDY_O = wGReady[0] & wGReady[1] & wGReady[2] & wGReady[3];
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assign GRDY_O = wGReady[0] & wGReady[1] & wGReady[2] & wGReady[3] & wGReady[4] & wGReady[5] & wGReady[6] & wGReady[7] & wGReady[8] & wGReady[9] & wGReady[10] & wGReady[11] & wGReady[12] & wGReady[13] & wGReady[14] & wGReady[15];
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//----------------------------------------------------------------
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assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3] & wDone[4] & wDone[5] & wDone[6] & wDone[7] & wDone[8] & wDone[9] & wDone[10] & wDone[11] & wDone[12] & wDone[13] & wDone[14] & wDone[15];
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//The next secuencial logic just AND all the wDone signals
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//I know that it would be much more elgant to just do parallel:
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//assign DONE_O = wDone[0] & wDone[1] & ... & wDone[MAX_CORES-1];
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//However, I don't know how to achieve this with 'generate' statements
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//So coding a simple loop instead
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/*
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always @ (posedge CLK_I)
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begin : AND_DONE_SIGNALS
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integer k;
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DONE_O = wDone[0];
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for (k=0;k<=`MAX_CORES;k=k+1)
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DONE_O=DONE_O & wDone[k+1];
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end
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*/
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assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3]; //Replace this by a counter??
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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Module_BusArbitrer ARB1
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Module_BusArbitrer ARB1
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(
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(
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.Clock( CLK_I ),
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.Clock( CLK_I ),
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Line 149... |
.oBusSelect( wBusSelect )
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.oBusSelect( wBusSelect )
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);
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);
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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// assign DAT_O = wDAT_O[ wBusSelect ];
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// assign TGA_O = wTGA_O[ wBusSelect ];
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// assign ADR_O = wADR_O[ wBusSelect ];
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// assign STB_O = wSTB_O[ wBusSelect ];
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// assign WE_O = wWE_O[ wBusSelect ];
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assign ACK_O = wACK_O[ wBusSelect];
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assign ACK_O = wACK_O[ wBusSelect];
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wire [`WB_WIDTH-1:0] wDataOut[`MAX_CORES-1:0];
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wire [`WB_WIDTH-1:0] wDataOut[`MAX_CORES-1:0];
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assign OMEM_O = wDataOut[ OMBSEL_I ];
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assign OMEM_O = wDataOut[ OMBSEL_I ];
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.MST_I( wMST_I[i] ),
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.MST_I( wMST_I[i] ),
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.TGA_I( wTGA_I[i] ),
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.TGA_I( wTGA_I[i] ),
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.CREG_I( CREG_I ),
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.CREG_I( CREG_I ),
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//Master Signals
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//Master Signals
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//.WE_O ( wWE_O[i] ),
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//.STB_O( wSTB_O[i] ),
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.ACK_O( wACK_O[i] ),
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.ACK_O( wACK_O[i] ),
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// .DAT_O( wDAT_O[i] ),
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//.ADR_O( wADR_O[i] ),
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.CYC_O( wBusRequest[i] ),
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.CYC_O( wBusRequest[i] ),
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.GNT_I( wBusGranted[i] ),
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.GNT_I( wBusGranted[i] ),
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//.TGA_O( wTGA_O[i] ),
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`ifdef DEBUG
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`ifdef DEBUG
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.iDebug_CoreID( i ),
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.iDebug_CoreID( i ),
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`endif
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`endif
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.OMEM_WE_O( wOMem_WE[i] ),
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.OMEM_WE_O( wOMem_WE[i] ),
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.OMEM_ADR_O( wOMEM_Address[i] ),
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.OMEM_ADR_O( wOMEM_Address[i] ),
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.OMEM_DAT_O( wOMEM_Dat[i] ),
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.OMEM_DAT_O( wOMEM_Dat[i] ),
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.TMEM_DAT_I( wCrossBarDataCollumn[i] ),
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.TMEM_DAT_I( wCrossBarDataCollumn[i] ),
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.TMEM_ADR_O( wTMemReadAdr[i] ),
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.TMEM_ADR_O( wTMemReadAdr[i] ),
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.TMEM_CYC_O( wCORE_2_TMEM__Req[i] ),
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.TMEM_CYC_O( wCORE_2_TMEM__Req[i] ),
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.TMEM_GNT_I( wTMEM_2_Core__Grant[i] ),
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.TMEM_GNT_I( wTMEM_2_Core__Grant[i] ),
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.Initial( 1'b0 ),
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.Initial( 1'b0 ),
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.Enable( wGRDY_O[i] ),
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.Enable( wGRDY_O[i] ),
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.Q(wGReady[i])
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.Q(wGReady[i])
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);
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);
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RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 500000 ) OMEM //10k mem
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RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 250000 ) OMEM //500000 ) OMEM
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(
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(
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.Clock( CLK_I ),
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.Clock( CLK_I ),
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.iWriteEnable( wOMem_WE[i] ),
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.iWriteEnable( wOMem_WE[i] ),
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.iWriteAddress( wOMEM_Address[i] ),
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.iWriteAddress( wOMEM_Address[i] ),
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.iDataIn( wOMEM_Dat[i] ),
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.iDataIn( wOMEM_Dat[i] ),
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Line 247... |
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//Each core has 1 bank request slot
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//Each core has 1 bank request slot
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//Each slot has MAX_TMEM_BANKS bits. Only 1 bit can
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//Each slot has MAX_TMEM_BANKS bits. Only 1 bit can
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//be 1 at any given point in time. All bits zero means,
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//be 1 at any given point in time. All bits zero means,
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//we are not requesting to read from any memory bank.
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//we are not requesting to read from any memory bank.
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SELECT_1_TO_N # ( 8, 4 ) READDRQ
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SELECT_1_TO_N # ( `WIDTH, `MAX_CORES ) READDRQ
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(
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(
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.Sel(wCoreBankSelect[ i]),
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.Sel(wCoreBankSelect[ i]),
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.En(wCORE_2_TMEM__Req[i]),
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.En(wCORE_2_TMEM__Req[i]),
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.O(wBankReadRequest[i])
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.O(wBankReadRequest[i])
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);
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);
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//The address coming from the core is virtual adress, meaning it assumes linear
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//The address coming from the core is virtual adress, meaning it assumes linear
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//address space, however, since memory is interleaved in a n-way memory we transform
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//address space, however, since memory is interleaved in a n-way memory we transform
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//virtual adress into physical adress (relative to the bank) like this
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//virtual adress into physical adress (relative to the bank) like this
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//fadr = vadr / n = vadr >> log2(n)
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//fadr = vadr / n = vadr >> log2(n)
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assign wCrossBarAdressCollumn[i] = (wTMemReadAdr[i] >> ((`MAX_TMEM_BANKS)/2));
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assign wCrossBarAdressCollumn[i] = (wTMemReadAdr[i] >> `MAX_CORE_BITS);
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//Connect the granted signal to Arbiter of the Bank we want to read from
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//Connect the granted signal to Arbiter of the Bank we want to read from
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assign wTMEM_2_Core__Grant[i] = wBankReadGranted[wCoreBankSelect[i]][i];
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assign wTMEM_2_Core__Grant[i] = wBankReadGranted[wCoreBankSelect[i]][i];
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//Connect the request signal to Arbiter of the Bank we want to read from
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//Connect the request signal to Arbiter of the Bank we want to read from
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Line 297... |
wire [`MAX_CORES-1:0] wBankReadGrantedDelay[`MAX_TMEM_BANKS-1:0];
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wire [`MAX_CORES-1:0] wBankReadGrantedDelay[`MAX_TMEM_BANKS-1:0];
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Module_BusArbitrer ARB_TMEM
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Module_BusArbitrer ARB_TMEM
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(
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(
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.Clock( CLK_I ),
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.Clock( CLK_I ),
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.Reset( RST_I ),
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.Reset( RST_I ),
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.iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),//wBankReadRequest[Bank] ), //The cores requesting to read from this Bank
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.iRequest( {wBankReadRequest[15][Bank],wBankReadRequest[14][Bank],wBankReadRequest[13][Bank],wBankReadRequest[12][Bank],wBankReadRequest[11][Bank],wBankReadRequest[10][Bank],wBankReadRequest[9][Bank],wBankReadRequest[8][Bank],wBankReadRequest[7][Bank],wBankReadRequest[6][Bank],wBankReadRequest[5][Bank],wBankReadRequest[4][Bank],wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),
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.oGrant( wBankReadGrantedDelay[Bank] ), //The bit of the core granted to read from this Bank
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.oGrant( wBankReadGrantedDelay[Bank] ), //The bit of the core granted to read from this Bank
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.oBusSelect( wCurrentCoreSelected[Bank] ) //The index of the core granted to read from this Bank
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.oBusSelect( wCurrentCoreSelected[Bank] ) //The index of the core granted to read from this Bank
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);
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);
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