| Line 81... |
Line 81... |
|
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
|
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
|
(
|
(
|
input wire [1:0] Sel,
|
input wire [1:0] Sel,
|
input wire [SIZE-1:0]I1, I2, I3,
|
input wire [SIZE-1:0]I1, I2, I3,
|
| Line 343... |
Line 344... |
Q <= D;
|
Q <= D;
|
|
|
endmodule
|
endmodule
|
|
|
//------------------------------------------------
|
//------------------------------------------------
|
module FF_OPCODE_POSEDGE_SYNCRONOUS_RESET
|
/*
|
(
|
module FF_OPCODE_POSEDGE_SYNCRONOUS_RESET
|
input wire Clock,
|
(
|
input wire Clear,
|
input wire Clock,
|
input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
|
input wire Clear,
|
output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
|
input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
|
);
|
output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
|
|
);
|
|
|
always @(posedge Clock or posedge Clear)
|
always @(posedge Clock or posedge Clear)
|
begin
|
begin
|
if (Clear)
|
if (Clear)
|
Q = `INSTRUCTION_OP_LENGTH'b0;
|
Q = `INSTRUCTION_OP_LENGTH'b0;
|
else
|
else
|
Q = D;
|
Q = D;
|
end
|
end
|
endmodule
|
endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
module FF32_POSEDGE_SYNCRONOUS_RESET
|
|
(
|
|
input wire Clock,
|
|
input wire Clear,
|
|
input wire[31:0] D,
|
|
output reg[31:0] Q
|
|
);
|
|
|
|
always @(posedge Clock or posedge Clear)
|
module FF32_POSEDGE_SYNCRONOUS_RESET
|
begin
|
(
|
if (Clear)
|
input wire Clock,
|
Q = 32'b0;
|
input wire Clear,
|
else
|
input wire[31:0] D,
|
Q = D;
|
output reg[31:0] Q
|
end
|
);
|
endmodule
|
|
//------------------------------------------------
|
|
|
|
module FF16_POSEDGE_SYNCRONOUS_RESET
|
always @(posedge Clock or posedge Clear)
|
(
|
begin
|
input wire Clock,
|
if (Clear)
|
input wire Clear,
|
Q = 32'b0;
|
input wire[15:0] D,
|
else
|
output reg[15:0] Q
|
Q = D;
|
);
|
end
|
|
endmodule
|
|
//------------------------------------------------
|
|
|
always @(posedge Clock or posedge Clear)
|
module FF16_POSEDGE_SYNCRONOUS_RESET
|
begin
|
(
|
if (Clear)
|
input wire Clock,
|
Q = 16'b0;
|
input wire Clear,
|
else
|
input wire[15:0] D,
|
Q = D;
|
output reg[15:0] Q
|
end
|
);
|
endmodule
|
|
|
|
|
always @(posedge Clock or posedge Clear)
|
|
begin
|
|
if (Clear)
|
|
Q = 16'b0;
|
|
else
|
|
Q = D;
|
|
end
|
|
endmodule
|
|
*/
|
//------------------------------------------------
|
//------------------------------------------------
|
module MUXFULLPARALELL_96bits_2SEL
|
module MUXFULLPARALELL_96bits_2SEL
|
(
|
(
|
input wire Sel,
|
input wire Sel,
|
input wire [95:0]I1, I2,
|
input wire [95:0]I1, I2,
|
