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https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk
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end
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end
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end
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end
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endmodule
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endmodule
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//------------------------------------------------
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module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
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module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
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(
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(
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input wire [1:0] Sel,
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input wire [1:0] Sel,
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input wire [SIZE-1:0]I1, I2, I3,
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input wire [SIZE-1:0]I1, I2, I3,I4,
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output reg [SIZE-1:0] O1
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output reg [SIZE-1:0] O1
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);
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);
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always @( * )
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always @( * )
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case (Sel)
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case (Sel)
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2'b00: O1 = I1;
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2'b00: O1 = I1;
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2'b01: O1 = I2;
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2'b01: O1 = I2;
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2'b10: O1 = I3;
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2'b10: O1 = I3;
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2'b11: O1 = I4;
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default: O1 = SIZE-1'b0;
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default: O1 = SIZE-1'b0;
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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//--------
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module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
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( input wire Clock,
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input wire Reset,
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input wire[SIZE-1:0] Initial,
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input wire Enable,
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output wire[SIZE-1:0] O
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);
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reg [SIZE-1:0] tmp;
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always @(posedge Clock)
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begin
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if (Reset)
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tmp <= Initial;
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else
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begin
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if (Enable)
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begin
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if (tmp[SIZE-1])
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tmp <= Initial;
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else
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tmp <= tmp << 1;
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end
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end
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end
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assign O = tmp;
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endmodule
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//------------------------------------------------
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//------------------------------------------------
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module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
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module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
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(
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(
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input wire [2:0] Sel,
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input wire [2:0] Sel,
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input wire [SIZE-1:0]I1, I2, I3,
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input wire [SIZE-1:0]I1, I2, I3,
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