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[/] [theia_gpu/] [branches/] [gpu_8_cores/] [rtl/] [Collaterals/] [Collaterals.v] - Diff between revs 76 and 104

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Rev 76 Rev 104
Line 82... Line 82... 
                end
 
                end
 
  end
 
  end
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
//----------------------------------------------------------------------
 
 
 
 
 
 
 
module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )
 
 
 
 (
 
 
 
 input wire [SEL_WIDTH-1:0] Sel,
 
 
 
 input wire  En,
 
 
 
 output wire [OUTPUT_WIDTH-1:0] O
 
 
 
 );
 
 
 
 
 
 
 
reg[OUTPUT_WIDTH-1:0] shift;
 
 
 
 
 
 
 
always @ ( * )
 
 
 
begin
 
 
 
        if (~En)
 
 
 
                shift = 1;
 
 
 
        else
 
 
 
                shift = (1 <<   Sel);
 
 
 
 
 
 
 
 
 
 
 
end
 
 
 
 
 
 
 
assign O = ( ~En ) ? 0 : shift ;
 
 
 
 
 
 
 
//assign O = En & (1 << Sel);
 
 
 
 
 
 
 
endmodule
 
 
 
 
 
 
 
//----------------------------------------------------------------------
 
 
 
 
 
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
 
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
 
 (
 
 (
 
 input wire [1:0] Sel,
 
 input wire [1:0] Sel,
 
 input wire [SIZE-1:0]I1, I2, I3,I4,
 
 input wire [SIZE-1:0]I1, I2, I3,I4,
Line 108... Line 136... 
 
 
 
 
  end
 
  end
 
 
 
 
 
endmodule
 
endmodule
 
 
 
 
 
 
 
/*
 
 
 
module MUXFULLPARALELL_CORESELECT # ( parameter SIZE=`WIDTH )
 
 
 
 (
 
 
 
 input wire [`MAX_CORES-1:0] Sel,
 
 
 
 input wire [SIZE-1:0] I1[`MAX_CORES-1:0],
 
 
 
 output reg [SIZE-1:0] O1
 
 
 
 );
 
 
 
 
 
 
 
always @( * )
 
 
 
 
 
 
 
  begin
 
 
 
 
 
 
 
    case (Sel)
 
 
 
        genvar i;
 
 
 
   generate
 
 
 
                for (i = 0; i < `MAX_CORES; i = i +1)
 
 
 
                begin : CORE
 
 
 
                        `MAX_CORES'di: O1 = I1[i];
 
 
 
 
 
 
 
 
 
 
 
                end
 
 
 
        endgenerate
 
 
 
         default: O1 = SIZE-1'b0;
 
 
 
    endcase
 
 
 
 
 
 
 
  end
 
 
 
 
 
 
 
endmodule
 
 
 
*/
 
//--------
 
//--------
 
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
 
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
 
( input wire Clock,
 
( input wire Clock,
 
  input wire Reset,
 
  input wire Reset,
 
  input wire[SIZE-1:0] Initial,
 
  input wire[SIZE-1:0] Initial,
Line 129... Line 186... 
        else
 
        else
 
        begin
 
        begin
 
                if (Enable)
 
                if (Enable)
 
                begin
 
                begin
 
                        if (tmp[SIZE-1])
 
                        if (tmp[SIZE-1])
 
 
 
                        begin
 
                                tmp <= Initial;
 
                                tmp <= Initial;
 
 
 
                        end
 
                        else
 
                        else
 
 
 
                        begin
 
                                tmp <= tmp << 1;
 
                                tmp <= tmp << 1;
 
                end
 
                end
 
        end
 
        end
 
  end
 
  end
 
 
 
  end
 
 
 
 
 
 
 
 
 
    assign O  = tmp;
 
    assign O  = tmp;
 
endmodule
 
endmodule
 
//------------------------------------------------
 
//------------------------------------------------

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