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| Rev 36 |
Rev 63 |
| Line 377... |
Line 377... |
else
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else
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Q = D;
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Q = D;
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end
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end
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endmodule
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endmodule
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//------------------------------------------------
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//------------------------------------------------
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module FF16_POSEDGE_SYNCRONOUS_RESET
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module FF16_POSEDGE_SYNCRONOUS_RESET
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Clear,
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input wire Clear,
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input wire[15:0] D,
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input wire[15:0] D,
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Line 473... |
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endmodule
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endmodule
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//------------------------------------------------
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//------------------------------------------------
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module MUXFULLPARALELL_1Bit_1SEL
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/*
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(
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module MUXFULLPARALELL_1Bit_1SEL
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input wire Sel,
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(
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input wire I1, I2,
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input wire Sel,
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output reg O1
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input wire I1, I2,
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);
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output reg O1
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);
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always @( * )
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always @( * )
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begin
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begin
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case (Sel)
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case (Sel)
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1'b0: O1 = I1;
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1'b0: O1 = I1;
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1'b1: O1 = I2;
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1'b1: O1 = I2;
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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*/
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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module FFD_OPCODE_POSEDGE
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/*
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(
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module FFD_OPCODE_POSEDGE
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input wire Clock,
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(
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input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
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input wire Clock,
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output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
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input wire[`INSTRUCTION_OP_LENGTH-1:0] D,
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);
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output reg[`INSTRUCTION_OP_LENGTH-1:0] Q
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);
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always @ (posedge Clock)
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always @ (posedge Clock)
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Q <= D;
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Q <= D;
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endmodule
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endmodule
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*/
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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module FFD16_POSEDGE
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/*
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(
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module FFD16_POSEDGE
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input wire Clock,
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(
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input wire[15:0] D,
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input wire Clock,
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output reg[15:0] Q
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input wire[15:0] D,
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);
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output reg[15:0] Q
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);
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always @ (posedge Clock)
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always @ (posedge Clock)
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Q <= D;
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Q <= D;
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endmodule
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endmodule
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*/
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//--------------------------------------------------------------
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//--------------------------------------------------------------
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module FFT1
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module FFT1
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(
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(
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input wire D,
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input wire D,
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