URL
https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 70 |
Rev 76 |
| Line 82... |
Line 82... |
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
//------------------------------------------------
|
|
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
|
module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
|
(
|
(
|
input wire [1:0] Sel,
|
input wire [1:0] Sel,
|
input wire [SIZE-1:0]I1, I2, I3,
|
input wire [SIZE-1:0]I1, I2, I3,I4,
|
output reg [SIZE-1:0] O1
|
output reg [SIZE-1:0] O1
|
);
|
);
|
|
|
always @( * )
|
always @( * )
|
|
|
| Line 99... |
Line 99... |
case (Sel)
|
case (Sel)
|
|
|
2'b00: O1 = I1;
|
2'b00: O1 = I1;
|
2'b01: O1 = I2;
|
2'b01: O1 = I2;
|
2'b10: O1 = I3;
|
2'b10: O1 = I3;
|
|
2'b11: O1 = I4;
|
default: O1 = SIZE-1'b0;
|
default: O1 = SIZE-1'b0;
|
|
|
endcase
|
endcase
|
|
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
|
//--------
|
|
module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
|
|
( input wire Clock,
|
|
input wire Reset,
|
|
input wire[SIZE-1:0] Initial,
|
|
input wire Enable,
|
|
output wire[SIZE-1:0] O
|
|
);
|
|
|
|
reg [SIZE-1:0] tmp;
|
|
|
|
|
|
always @(posedge Clock)
|
|
begin
|
|
if (Reset)
|
|
tmp <= Initial;
|
|
else
|
|
begin
|
|
if (Enable)
|
|
begin
|
|
if (tmp[SIZE-1])
|
|
tmp <= Initial;
|
|
else
|
|
tmp <= tmp << 1;
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
assign O = tmp;
|
|
endmodule
|
//------------------------------------------------
|
//------------------------------------------------
|
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
|
module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
|
(
|
(
|
input wire [2:0] Sel,
|
input wire [2:0] Sel,
|
input wire [SIZE-1:0]I1, I2, I3,
|
input wire [SIZE-1:0]I1, I2, I3,
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.