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[/] [theia_gpu/] [branches/] [gpu_8_cores/] [rtl/] [Collaterals/] [aDefinitions.v] - Diff between revs 128 and 129

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Rev 128	Rev 129
Line 26...	Line 26...
`all over the code. By now you have may noticed that all`	`all over the code. By now you have may noticed that all`
`constants are pre-compilation define directives. This is`	`constants are pre-compilation define directives. This is`
`for simulation perfomance reasons mainly.`	`for simulation perfomance reasons mainly.`
`*******************************************************************************/`	`*******************************************************************************/`

`define MAX_CORES 4 //The number of cores, make sure you update MAX_CORE_BITS!	`define MAX_CORES 8 //The number of cores, make sure you update MAX_CORE_BITS!
`define MAX_CORE_BITS 2 // 2 ^ MAX_CORE_BITS = MAX_CORES	`define MAX_CORE_BITS 3 // 2 ^ MAX_CORE_BITS = MAX_CORES
`define MAX_TMEM_BANKS 4 //The number of memory banks for TMEM	`define MAX_TMEM_BANKS 8 //The number of memory banks for TMEM
`//---------------------------------------------------------------------------------`	`//---------------------------------------------------------------------------------`
//Verilog provides a `default_nettype none compiler directive. When	//Verilog provides a `default_nettype none compiler directive. When
`//this directive is set, implicit data types are disabled, which will make any`	`//this directive is set, implicit data types are disabled, which will make any`
`//undeclared signal name a syntax error.This is very usefull to avoid annoying`	`//undeclared signal name a syntax error.This is very usefull to avoid annoying`
`//automatic 1 bit long wire declaration where you don't want them to be!`	`//automatic 1 bit long wire declaration where you don't want them to be!`

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