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[/] [theia_gpu/] [branches/] [icarus_version/] [rtl/] [Collaterals.v] - Diff between revs 174 and 175

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Rev 174 Rev 175
Line 20... Line 20...
You should have received a copy of the GNU General Public License
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 
 
***********************************************************************************/
***********************************************************************************/
//------------------------------------------------
 
module FFD_POSEDGE_ASYNC_RESET # ( parameter SIZE=`WIDTH )
 
        (
 
        input wire Clock,
 
        input wire Clear,
 
        input wire [SIZE-1:0] D,
 
        output reg [SIZE-1:0] Q
 
        );
 
 
 
  always @(posedge Clock or posedge Clear)
 
    begin
 
           if (Clear)
 
        Q = 0;
 
      else
 
        Q = D;
 
    end
 
endmodule
 
//----------------------------------------------------
//----------------------------------------------------
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
(
(
        input wire                              Clock,
        input wire                              Clock,
        input wire                              Reset,
        input wire                              Reset,
Line 51... Line 35...
 
 
 
 
always @ (posedge Clock)
always @ (posedge Clock)
begin
begin
        if ( Reset )
        if ( Reset )
                Q <= `WIDTH'b0;
                Q <= {SIZE{1'b0}};
        else
        else
        begin
        begin
                if (Enable)
                if (Enable)
                        Q <= D;
                        Q <= D;
        end
        end
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      2'b00: O1 = I1;
      2'b00: O1 = I1;
      2'b01: O1 = I2;
      2'b01: O1 = I2;
                2'b10: O1 = I3;
                2'b10: O1 = I3;
                2'b11: O1 = I4;
                2'b11: O1 = I4;
                default: O1 = SIZE-1'b0;
                default: O1 = SIZE;
 
 
    endcase
    endcase
 
 
  end
  end
 
 
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    case (Sel)
    case (Sel)
 
 
      3'b001: O1 = I1;
      3'b001: O1 = I1;
      3'b010: O1 = I2;
      3'b010: O1 = I2;
                3'b100: O1 = I3;
                3'b100: O1 = I3;
                default: O1 = SIZE-1'b0;
      default: O1 = SIZE;
 
 
    endcase
    endcase
 
 
  end
  end
 
 

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