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Rev 176 |
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Line 97... |
//assign O = En & (1 << Sel);
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//assign O = En & (1 << Sel);
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endmodule
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endmodule
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//----------------------------------------------------------------------
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//----------------------------------------------------------------------
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module MUXFULLPARALELL_GENERIC #(parameter WIDTH = `WIDTH, parameter CHANNELS = 4, parameter SELBITS = 2)
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(
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input wire [(CHANNELS*WIDTH)-1:0] in_bus,
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input wire [SELBITS-1:0] sel,
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output wire [WIDTH-1:0] out
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);
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genvar ig;
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wire [WIDTH-1:0] input_array [0:CHANNELS-1];
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assign out = input_array[sel];
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generate
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for(ig=0; ig<CHANNELS; ig=ig+1)
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begin: array_assignments
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assign input_array[ig] = in_bus[(ig*WIDTH)+:WIDTH];
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end
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endgenerate
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endmodule
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//----------------------------------------------------------------------
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module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
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module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
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(
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(
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input wire [1:0] Sel,
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input wire [1:0] Sel,
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input wire [SIZE-1:0]I1, I2, I3,I4,
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input wire [SIZE-1:0]I1, I2, I3,I4,
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output reg [SIZE-1:0] O1
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output reg [SIZE-1:0] O1
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