| Line 185... |
Line 185... |
// dividend placed initially so that remainder bits are zero...
|
// dividend placed initially so that remainder bits are zero...
|
grand_dividend <= dividend_i << R_PP;
|
grand_dividend <= dividend_i << R_PP;
|
// divisor placed initially for a 1 bit overlap with dividend...
|
// divisor placed initially for a 1 bit overlap with dividend...
|
// But adjust it back by S_PP, to account for bits that are known
|
// But adjust it back by S_PP, to account for bits that are known
|
// to be leading zeros in the quotient.
|
// to be leading zeros in the quotient.
|
|
/* verilator lint_off WIDTH */
|
grand_divisor <= divisor_i << (N_PP+R_PP-S_PP-1);
|
grand_divisor <= divisor_i << (N_PP+R_PP-S_PP-1);
|
|
/* verilator lint_on WIDTH */
|
end
|
end
|
|
/* verilator lint_off WIDTH */
|
else if (divide_count == M_PP+R_PP-S_PP-1)
|
else if (divide_count == M_PP+R_PP-S_PP-1)
|
|
/* verilator lint_on WIDTH */
|
begin
|
begin
|
if (~done_o) quotient <= quotient_node; // final shift...
|
if (~done_o) quotient <= quotient_node; // final shift...
|
if (~done_o) quotient_reg <= quotient_node; // final shift (held output)
|
if (~done_o) quotient_reg <= quotient_node; // final shift (held output)
|
done_o <= 1; // Indicate done, just sit
|
done_o <= 1; // Indicate done, just sit
|
end
|
end
|
else // Division in progress
|
else // Division in progress
|
begin
|
begin
|
// If the subtraction yields a positive result, then store that result
|
// If the subtraction yields a positive result, then store that result
|
|
/* verilator lint_off WIDTH */
|
if (~subtract_node[M_PP+N_PP+R_PP-1]) grand_dividend <= subtract_node;
|
if (~subtract_node[M_PP+N_PP+R_PP-1]) grand_dividend <= subtract_node;
|
|
/* verilator lint_on WIDTH */
|
// If the subtraction yields a positive result, then a 1 bit goes into
|
// If the subtraction yields a positive result, then a 1 bit goes into
|
// the quotient, via a shift register
|
// the quotient, via a shift register
|
quotient <= quotient_node;
|
quotient <= quotient_node;
|
// shift the grand divisor to the right, to cut it in half next clock cycle
|
// shift the grand divisor to the right, to cut it in half next clock cycle
|
grand_divisor <= divisor_node;
|
grand_divisor <= divisor_node;
|
| Line 208... |
Line 214... |
divide_count <= divide_count + 1;
|
divide_count <= divide_count + 1;
|
end
|
end
|
end // End of else if clk_en_i
|
end // End of else if clk_en_i
|
end // End of always block
|
end // End of always block
|
|
|
|
/* verilator lint_off WIDTH */
|
assign subtract_node = {1'b0,grand_dividend} - {1'b0,grand_divisor};
|
assign subtract_node = {1'b0,grand_dividend} - {1'b0,grand_divisor};
|
|
/* verilator lint_on WIDTH */
|
assign quotient_node =
|
assign quotient_node =
|
{quotient[M_PP+R_PP-S_PP-2:0],~subtract_node[M_PP+N_PP+R_PP-1]};
|
{quotient[M_PP+R_PP-S_PP-2:0],~subtract_node[M_PP+N_PP+R_PP-1]};
|
assign divisor_node = {1'b0,grand_divisor[M_PP+N_PP+R_PP-2:1]};
|
assign divisor_node = {1'b0,grand_divisor[M_PP+N_PP+R_PP-2:1]};
|
|
|
assign quotient_o = (HELD_OUTPUT_PP == 0)?quotient:quotient_reg;
|
assign quotient_o = (HELD_OUTPUT_PP == 0)?quotient:quotient_reg;
|
