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Line 1... |
`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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`ifdef VERILATOR
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`include "Module_HostWBM.v"
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`endif
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Line 76... |
output wire [`WB_WIDTH-1:0] oReadAddress,
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output wire [`WB_WIDTH-1:0] oReadAddress,
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input wire [`WB_WIDTH-1:0] iReadData,
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input wire [`WB_WIDTH-1:0] iReadData,
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input wire iGPUCommitedResults,
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input wire iGPUCommitedResults,
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//To Hub/Switch
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//To Hub/Switch
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output wire [`MAX_CORES-1:0] oCoreSelectMask,
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output reg [`MAX_CORES-1:0] oCoreSelectMask,
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output reg [1:0] oMemSelect,
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output reg [1:0] oMemSelect,
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output wire [`WB_WIDTH-1:0] DAT_O,
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output wire [`WB_WIDTH-1:0] DAT_O,
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output wire [`WB_WIDTH-1:0] ADR_O,
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output wire [`WB_WIDTH-1:0] ADR_O,
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output reg[1:0] TGA_O,
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output reg[1:0] TGA_O,
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output reg[`MAX_CORES-1:0] RENDREN_O,
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output reg[`MAX_CORES-1:0] RENDREN_O,
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| Line 92... |
Line 94... |
output reg oHostDataAvailable,
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output reg oHostDataAvailable,
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input wire iGPUDone,
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input wire iGPUDone,
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`ifndef NO_DISPLAY_STATS
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`ifndef NO_DISPLAY_STATS
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input wire [`WIDTH-1:0] iDebugWidth,
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input wire [`WIDTH-1:0] iDebugWidth,
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`endif
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`endif
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input wire ACK_I
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input wire ACK_I
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);
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);
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wire wGPUDone;
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//Need this flop to break combinatorial loop asserted by verilator!
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD_DONE
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(
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.Clock(Clock),
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.Reset(Reset),
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.Enable( 1'b1 ),
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.D(iGPUDone),
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.Q(wGPUDone)
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);
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//---------------------------------------------------------------
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//---------------------------------------------------------------
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wire wLastPrimitive;
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wire wLastPrimitive;
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assign wLastPrimitive = (wVertexCount >= iPrimitiveCount) ? 1'b1 : 1'b0;
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assign wLastPrimitive = (wVertexCount >= iPrimitiveCount) ? 1'b1 : 1'b0;
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assign STDONE_O = wLastPrimitive;
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assign STDONE_O = wLastPrimitive;
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| Line 113... |
Line 129... |
reg rIncCoreSelect,rResetVertexCount;
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reg rIncCoreSelect,rResetVertexCount;
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//--------------------------------------------------------
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//--------------------------------------------------------
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assign WE_O = MST_O;
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assign WE_O = MST_O;
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assign oCoreSelectMask =
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//assign oCoreSelectMask =
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(rCoreBroadCast) ? `SELECT_ALL_CORES : wCoreSelect;
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// (rCoreBroadCast) ? `SELECT_ALL_CORES : wCoreSelect;
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wire wLastCoreSelected;
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assign wLastCoreSelected = wCoreSelect[`MAX_CORES-1];
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assign wLastValidReadAddress =
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assign wLastValidReadAddress =
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(oReadAddress >= iMemorySize) ? 1'b1 : 1'b0;
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(oReadAddress >= iMemorySize) ? 1'b1 : 1'b0;
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wire wLastParameter;
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wire wLastParameter;
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Line 175... |
wire wShortCycle;
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wire wShortCycle;
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//For instruction we send 2 packets per cycle
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//For instruction we send 2 packets per cycle
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//for the other we send 3 packets per cycle
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//for the other we send 3 packets per cycle
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assign wShortCycle = (oMemSelect == `SELECT_INST_MEM) ? 1'b1 : 1'b0;
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assign wShortCycle = (oMemSelect == `SELECT_INST_MEM) ? 1'b1 : 1'b0;
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WBMaster WBM
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WBMaster HOST_WBM
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset | rWBMReset ),
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.Reset( Reset | rWBMReset ),
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.iEnable( rWBMEnable ),
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.iEnable( rWBMEnable ),
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.iInitialReadAddr( rInitiaReadAddr ),
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.iInitialReadAddr( rInitiaReadAddr ),
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Line 213... |
reg [63:0] RenderedPixels;
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reg [63:0] RenderedPixels;
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wire wLastVertexInFrame;
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wire wLastVertexInFrame;
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assign wLastVertexInFrame =
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assign wLastVertexInFrame =
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(wVertexCount % `MAX_VERTEX_IN_FRAME == 1'b0 ) ? 1'b1 : 1'b0;
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(wVertexCount % `MAX_VERTEX_IN_FRAME == 1'b0 ) ? 1'b1 : 1'b0;
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// WAS ((wVertexCount % `MAX_VERTEX_IN_FRAME) == 1'b0 && wVertexCount != 0) ? 1'b1 : 1'b0;
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reg [31:0] StartTime;
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reg [31:0] StartTime;
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// Host Finite State Machine //
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// Host Finite State Machine //
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always @( * )
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always @( * )
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Line 226... |
//----------------------------------------
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//----------------------------------------
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//Wait for reset sequence to complete,
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//Wait for reset sequence to complete,
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//Or until we are enabled
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//Or until we are enabled
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`HOST_IDLE:
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`HOST_IDLE:
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begin
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begin
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`ifndef VERILATOR
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RenderedPixels = 0;
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RenderedPixels = 0;
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`endif
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rWBMEnable = 0;
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rWBMEnable = 0;
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rInitiaReadAddr = 1; //Start reading from 1, because 0 is the size
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rInitiaReadAddr = 1; //Start reading from 1, because 0 is the size
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rWBMReset = 0;
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rWBMReset = 0;
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oMemSelect = 0;
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oMemSelect = 0;
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TGA_O = 0;
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TGA_O = 0;
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MST_O = 0;
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MST_O = 0;
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rInitialWriteAddress = 0;
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rInitialWriteAddress = 0;
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rSetWriteAddr = 0;
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rSetWriteAddr = 0;
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rCoreBroadCast = 0;
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//rCoreBroadCast = 0;
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oCoreSelectMask = wCoreSelect;
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rIncCoreSelect = 0;
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rIncCoreSelect = 0;
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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//STDONE_O = 0;
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oHostDataAvailable = 0;
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oHostDataAvailable = 0;
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if ( ~Reset & iEnable )
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if ( ~Reset & iEnable )
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begin
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begin
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$display("-I- HOST: Broadcasting User code to all Cores\n"); $fflush;
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$display("-I- HOST: Broadcasting User code to all Cores\n");
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`ifndef VERILATOR
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$fflush;
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`endif
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rHostNextState = `HOST_WRITE_INSTRUCTION;
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rHostNextState = `HOST_WRITE_INSTRUCTION;
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end
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end
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else
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else
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rHostNextState = `HOST_IDLE;
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rHostNextState = `HOST_IDLE;
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end
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end
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Line 273... |
oMemSelect = `SELECT_INST_MEM; //Start by sending the instructions
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oMemSelect = `SELECT_INST_MEM; //Start by sending the instructions
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TGA_O = `TAG_INSTRUCTION_ADDRESS_TYPE;
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TGA_O = `TAG_INSTRUCTION_ADDRESS_TYPE;
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MST_O = 1;
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MST_O = 1;
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rInitialWriteAddress = 0;
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rInitialWriteAddress = 0;
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rSetWriteAddr = 0;
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rSetWriteAddr = 0;
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rCoreBroadCast = 1;
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//rCoreBroadCast = 1;
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oCoreSelectMask = `SELECT_ALL_CORES;
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rIncCoreSelect = 0;
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rIncCoreSelect = 0;
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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//STDONE_O = 0;
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oHostDataAvailable = 0;
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oHostDataAvailable = 0;
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rHostNextState = `HOST_WAIT_INSTRUCTION;
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rHostNextState = `HOST_WAIT_INSTRUCTION;
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end
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end
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//----------------------------------------
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//----------------------------------------
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Line 294... |
oMemSelect = `SELECT_INST_MEM;
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oMemSelect = `SELECT_INST_MEM;
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TGA_O = `TAG_INSTRUCTION_ADDRESS_TYPE;
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TGA_O = `TAG_INSTRUCTION_ADDRESS_TYPE;
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MST_O = 1;
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MST_O = 1;
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rInitialWriteAddress = 0;
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rInitialWriteAddress = 0;
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rSetWriteAddr = 0;
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rSetWriteAddr = 0;
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rCoreBroadCast = 1;
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//rCoreBroadCast = 1;
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oCoreSelectMask = `SELECT_ALL_CORES;
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rIncCoreSelect = 0;
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rIncCoreSelect = 0;
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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//STDONE_O = 0;
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oHostDataAvailable = 0;
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oHostDataAvailable = 0;
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if ( wWBMDone && ~wLastValidReadAddress )
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if ( wWBMDone && ~wLastValidReadAddress )
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rHostNextState = `HOST_WRITE_INSTRUCTION;
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rHostNextState = `HOST_WRITE_INSTRUCTION;
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else if (wWBMDone && wLastValidReadAddress )
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else if (wWBMDone && wLastValidReadAddress )
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Line 324... |
oMemSelect = `SELECT_SCENE_MEM; //We are reading from the scene memory
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oMemSelect = `SELECT_SCENE_MEM; //We are reading from the scene memory
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TGA_O = `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
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TGA_O = `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
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MST_O = 1; //Keep master signal in 1 for now
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MST_O = 1; //Keep master signal in 1 for now
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rInitialWriteAddress = 0; //We start writing from address zero now
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rInitialWriteAddress = 0; //We start writing from address zero now
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rSetWriteAddr = 1;
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rSetWriteAddr = 1;
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rCoreBroadCast = 1; //Set to zero to unicast, starting from core 0
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//rCoreBroadCast = 1; //Set to zero to unicast, starting from core 0
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oCoreSelectMask = `SELECT_ALL_CORES;
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rIncCoreSelect = 0; //Set to unicast to the next core
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rIncCoreSelect = 0; //Set to unicast to the next core
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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//STDONE_O = 0;
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oHostDataAvailable = 0;
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oHostDataAvailable = 0;
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$display("-I- HOST: Configuring Core Mask %b\n",oCoreSelectMask); $fflush;
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$display("-I- HOST: Configuring Core Mask %b\n",oCoreSelectMask);
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`ifndef VERILATOR
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$fflush;
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`endif
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rHostNextState = `HOST_WRITE_SCENE_PARAMS;
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rHostNextState = `HOST_WRITE_SCENE_PARAMS;
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end
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end
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//----------------------------------------
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//----------------------------------------
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Line 353... |
oMemSelect = `SELECT_SCENE_MEM;
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oMemSelect = `SELECT_SCENE_MEM;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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MST_O = 1;
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MST_O = 1;
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rInitialWriteAddress = 0;
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rInitialWriteAddress = 0;
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rSetWriteAddr = 0;
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rSetWriteAddr = 0;
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rCoreBroadCast = 1;
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//rCoreBroadCast = 1;
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oCoreSelectMask = `SELECT_ALL_CORES;
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rIncCoreSelect = 0;
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rIncCoreSelect = 0;
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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//STDONE_O = 0;
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oHostDataAvailable = 0;
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oHostDataAvailable = 0;
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rHostNextState = `HOST_WAIT_SCENE_PARAMS;
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rHostNextState = `HOST_WAIT_SCENE_PARAMS;
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end
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end
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//----------------------------------------
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//----------------------------------------
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| Line 345... |
Line 374... |
oMemSelect = `SELECT_SCENE_MEM;
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oMemSelect = `SELECT_SCENE_MEM;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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MST_O = 1;
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MST_O = 1;
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rInitialWriteAddress = 0;
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rInitialWriteAddress = 0;
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rSetWriteAddr = 0;
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rSetWriteAddr = 0;
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rCoreBroadCast = 1;
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//rCoreBroadCast = 1;
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oCoreSelectMask = `SELECT_ALL_CORES;
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rIncCoreSelect = 0;
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rIncCoreSelect = 0;
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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//STDONE_O = 0;
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oHostDataAvailable = 0;
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oHostDataAvailable = 0;
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if ( wWBMDone && ~wLastParameter )
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if ( wWBMDone && ~wLastParameter )
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rHostNextState = `HOST_WRITE_SCENE_PARAMS;
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rHostNextState = `HOST_WRITE_SCENE_PARAMS;
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else if (wWBMDone && wLastParameter )
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else if (wWBMDone && wLastParameter )
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| Line 377... |
Line 406... |
oMemSelect = `SELECT_SCENE_MEM; //We are reading from the scene memory
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oMemSelect = `SELECT_SCENE_MEM; //We are reading from the scene memory
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TGA_O = `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
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TGA_O = `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
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MST_O = 1; //Keep master signal in 1 for now
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MST_O = 1; //Keep master signal in 1 for now
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rInitialWriteAddress = `CREG_PIXEL_2D_INITIAL_POSITION; //The address from which to start wrting @ the cores
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rInitialWriteAddress = `CREG_PIXEL_2D_INITIAL_POSITION; //The address from which to start wrting @ the cores
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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rCoreBroadCast = 0; //Set to zero to unicast, starting from core 0
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//rCoreBroadCast = 0; //Set to zero to unicast, starting from core 0
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oCoreSelectMask = wCoreSelect;
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rIncCoreSelect = 0; //Set to unicast to the next core
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rIncCoreSelect = 0; //Set to unicast to the next core
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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//STDONE_O = 0;
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oHostDataAvailable = 0;
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oHostDataAvailable = 0;
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rHostNextState = `HOST_UNICAST_CORE_CONFIG;
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rHostNextState = `HOST_UNICAST_CORE_CONFIG;
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end
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end
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| Line 400... |
Line 429... |
oMemSelect = `SELECT_SCENE_MEM;
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oMemSelect = `SELECT_SCENE_MEM;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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MST_O = 1;
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MST_O = 1;
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rInitialWriteAddress = 0;
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rInitialWriteAddress = 0;
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rSetWriteAddr = 0;
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rSetWriteAddr = 0;
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rCoreBroadCast = 0;
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//rCoreBroadCast = 0;
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oCoreSelectMask = wCoreSelect;
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rIncCoreSelect = 0;
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rIncCoreSelect = 0;
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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//STDONE_O = 0;
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oHostDataAvailable = 0;
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oHostDataAvailable = 0;
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rHostNextState = `HOST_WAIT_CORE_CONFIG;
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rHostNextState = `HOST_WAIT_CORE_CONFIG;
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end
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end
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//----------------------------------------
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//----------------------------------------
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| Line 421... |
Line 450... |
oMemSelect = `SELECT_SCENE_MEM;
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oMemSelect = `SELECT_SCENE_MEM;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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MST_O = 1;
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MST_O = 1;
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rInitialWriteAddress = 0;
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rInitialWriteAddress = 0;
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rSetWriteAddr = 0;
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rSetWriteAddr = 0;
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rCoreBroadCast = 0;
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//rCoreBroadCast = 0;
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oCoreSelectMask = wCoreSelect;
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rIncCoreSelect = 0;
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rIncCoreSelect = 0;
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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//STDONE_O = 0;
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oHostDataAvailable = 0;
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oHostDataAvailable = 0;
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if (wWBMDone && !(oReadAddress % 2))
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if (wWBMDone && !(oReadAddress % 2))
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rHostNextState = `HOST_UNICAST_CORE_CONFIG;
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rHostNextState = `HOST_UNICAST_CORE_CONFIG;
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| Line 453... |
Line 482... |
oMemSelect = `SELECT_GEO_MEM;
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oMemSelect = `SELECT_GEO_MEM;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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MST_O = 0; //The master signal goes to zero until request
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MST_O = 0; //The master signal goes to zero until request
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rInitialWriteAddress = `CREG_PIXEL_2D_INITIAL_POSITION; //Write starting from this location on the cores
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rInitialWriteAddress = `CREG_PIXEL_2D_INITIAL_POSITION; //Write starting from this location on the cores
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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rCoreBroadCast = 0;
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//rCoreBroadCast = 0;
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oCoreSelectMask = wCoreSelect;
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rIncCoreSelect = 1; //Moving to configure the next core now
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rIncCoreSelect = 1; //Moving to configure the next core now
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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//STDONE_O = 0;
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oHostDataAvailable = 0;
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oHostDataAvailable = 0;
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if (wCoreSelect[`MAX_CORES-1] == 1)
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if (wLastCoreSelected)//wCoreSelect[`MAX_CORES-1] == 1)
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rHostNextState = `HOST_PREPARE_FOR_GEO_REQUESTS;
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rHostNextState = `HOST_PREPARE_FOR_GEO_REQUESTS;
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else
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else
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rHostNextState = `HOST_UNICAST_CORE_CONFIG;
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rHostNextState = `HOST_UNICAST_CORE_CONFIG;
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end
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end
|
//----------------------------------------
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//----------------------------------------
|
| Line 481... |
Line 510... |
oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
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oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
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TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
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TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
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MST_O = 0; //The master signal goes to zero until request
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MST_O = 0; //The master signal goes to zero until request
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rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores
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rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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rCoreBroadCast = 1; //From now on we only broadcast
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//rCoreBroadCast = 1; //From now on we only broadcast
|
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oCoreSelectMask = `SELECT_ALL_CORES;
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rIncCoreSelect = 0; //Ignored during broadcasts
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rIncCoreSelect = 0; //Ignored during broadcasts
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 1;
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rResetVertexCount = 1;
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GACK_O = 0;
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GACK_O = 0;
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//STDONE_O = 0;
|
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oHostDataAvailable = 0;
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oHostDataAvailable = 0;
|
|
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if (iGPUDone)
|
if (wGPUDone)
|
rHostNextState = `HOST_GPU_EXECUTION_DONE;
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rHostNextState = `HOST_GPU_EXECUTION_DONE;
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else
|
else
|
rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
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rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
|
|
|
end
|
end
|
| Line 506... |
Line 535... |
oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
|
oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
|
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
|
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
|
MST_O = 0; //The master signal goes to zero until request
|
MST_O = 0; //The master signal goes to zero until request
|
rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores
|
rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores
|
rSetWriteAddr = 1; //Set to use the initial write address bellow
|
rSetWriteAddr = 1; //Set to use the initial write address bellow
|
rCoreBroadCast = 1; //From now on we only broadcast
|
//rCoreBroadCast = 1; //From now on we only broadcast
|
|
oCoreSelectMask = `SELECT_ALL_CORES;
|
rIncCoreSelect = 0; //Ignored during broadcasts
|
rIncCoreSelect = 0; //Ignored during broadcasts
|
RENDREN_O = 0;
|
RENDREN_O = 0;
|
rResetVertexCount = 0;
|
rResetVertexCount = 0;
|
GACK_O = 1;
|
GACK_O = 1;
|
//STDONE_O = 0;
|
|
oHostDataAvailable = 0;
|
oHostDataAvailable = 0;
|
|
|
|
|
rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
|
rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
|
|
|
| Line 533... |
Line 562... |
oMemSelect = `SELECT_GEO_MEM;
|
oMemSelect = `SELECT_GEO_MEM;
|
TGA_O = `TAG_DATA_ADDRESS_TYPE;
|
TGA_O = `TAG_DATA_ADDRESS_TYPE;
|
MST_O = 1; //Start the Transmition
|
MST_O = 1; //Start the Transmition
|
rInitialWriteAddress = 0;
|
rInitialWriteAddress = 0;
|
rSetWriteAddr = 0;
|
rSetWriteAddr = 0;
|
rCoreBroadCast = 1;
|
//rCoreBroadCast = 1;
|
|
oCoreSelectMask = `SELECT_ALL_CORES;
|
rIncCoreSelect = 0;
|
rIncCoreSelect = 0;
|
RENDREN_O = `SELECT_ALL_CORES;
|
RENDREN_O = `SELECT_ALL_CORES;
|
rResetVertexCount = 0;
|
rResetVertexCount = 0;
|
GACK_O = 0;
|
GACK_O = 0;
|
//STDONE_O = 0;
|
|
oHostDataAvailable = 0;
|
oHostDataAvailable = 0;
|
|
|
rHostNextState = `HOST_WAIT_FOR_VERTEX;
|
rHostNextState = `HOST_WAIT_FOR_VERTEX;
|
|
|
end
|
end
|
| Line 555... |
Line 584... |
oMemSelect = `SELECT_GEO_MEM;
|
oMemSelect = `SELECT_GEO_MEM;
|
TGA_O = `TAG_DATA_ADDRESS_TYPE;
|
TGA_O = `TAG_DATA_ADDRESS_TYPE;
|
MST_O = 1; //Start the Transmition
|
MST_O = 1; //Start the Transmition
|
rInitialWriteAddress = 0;
|
rInitialWriteAddress = 0;
|
rSetWriteAddr = 0;
|
rSetWriteAddr = 0;
|
rCoreBroadCast = 1;
|
//rCoreBroadCast = 1;
|
|
oCoreSelectMask = `SELECT_ALL_CORES;
|
rIncCoreSelect = 0;
|
rIncCoreSelect = 0;
|
RENDREN_O = `SELECT_ALL_CORES;
|
RENDREN_O = `SELECT_ALL_CORES;
|
rResetVertexCount = 0;
|
rResetVertexCount = 0;
|
GACK_O = 0;
|
GACK_O = 0;
|
//STDONE_O = 0;
|
|
oHostDataAvailable = 0;
|
oHostDataAvailable = 0;
|
|
|
|
|
if (wWBMDone & ~wLastVertexInFrame )
|
if (wWBMDone & ~wLastVertexInFrame )
|
rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
|
rHostNextState = `HOST_BROADCAST_NEXT_VERTEX;
|
else if (wWBMDone & wLastVertexInFrame )
|
else if (wWBMDone & wLastVertexInFrame )
|
rHostNextState = `HOST_GET_PRIMITIVE_COUNT;
|
rHostNextState = `HOST_GET_PRIMITIVE_COUNT;
|
else
|
else
|
rHostNextState = `HOST_WAIT_FOR_VERTEX;
|
rHostNextState = `HOST_WAIT_FOR_VERTEX;
|
|
|
|
|
/*
|
|
if (wWBMDone)
|
|
rHostNextState = `HOST_WAIT_DATA_READ_CONFIRMATION;
|
|
else
|
|
rHostNextState = `HOST_WAIT_FOR_VERTEX;
|
|
*/
|
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
`HOST_GET_PRIMITIVE_COUNT:
|
`HOST_GET_PRIMITIVE_COUNT:
|
begin
|
begin
|
rWBMEnable = 0; //Disable WBM when it is donw
|
rWBMEnable = 0; //Disable WBM when it is donw
|
| Line 590... |
Line 612... |
oMemSelect = `SELECT_GEO_MEM;
|
oMemSelect = `SELECT_GEO_MEM;
|
TGA_O = `TAG_DATA_ADDRESS_TYPE;
|
TGA_O = `TAG_DATA_ADDRESS_TYPE;
|
MST_O = 1; //Start the Transmition
|
MST_O = 1; //Start the Transmition
|
rInitialWriteAddress = 0;
|
rInitialWriteAddress = 0;
|
rSetWriteAddr = 0;
|
rSetWriteAddr = 0;
|
rCoreBroadCast = 1;
|
//rCoreBroadCast = 1;
|
|
oCoreSelectMask = `SELECT_ALL_CORES;
|
rIncCoreSelect = 0;
|
rIncCoreSelect = 0;
|
RENDREN_O = `SELECT_ALL_CORES;
|
RENDREN_O = `SELECT_ALL_CORES;
|
rResetVertexCount = 0;
|
rResetVertexCount = 0;
|
GACK_O = 0;
|
GACK_O = 0;
|
//STDONE_O = 0;
|
|
oHostDataAvailable = 0;//1;
|
oHostDataAvailable = 0;//1;
|
|
|
if (wVertexCount >= iPrimitiveCount)
|
if (wVertexCount >= iPrimitiveCount)
|
rHostNextState = `HOST_LAST_PRIMITIVE_REACHED;
|
rHostNextState = `HOST_LAST_PRIMITIVE_REACHED;
|
else
|
else
|
| Line 620... |
Line 642... |
oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
|
oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
|
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
|
TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
|
MST_O = 0; //The master signal goes to zero until request
|
MST_O = 0; //The master signal goes to zero until request
|
rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores
|
rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores
|
rSetWriteAddr = 1; //Set to use the initial write address bellow
|
rSetWriteAddr = 1; //Set to use the initial write address bellow
|
rCoreBroadCast = 1; //From now on we only broadcast
|
//rCoreBroadCast = 1; //From now on we only broadcast
|
|
oCoreSelectMask = `SELECT_ALL_CORES;
|
rIncCoreSelect = 0; //Ignored during broadcasts
|
rIncCoreSelect = 0; //Ignored during broadcasts
|
RENDREN_O = `SELECT_ALL_CORES;
|
RENDREN_O = `SELECT_ALL_CORES;
|
rResetVertexCount = 0;
|
rResetVertexCount = 0;
|
GACK_O = 0;
|
GACK_O = 0;
|
//STDONE_O = 0;
|
|
oHostDataAvailable = 1;
|
oHostDataAvailable = 1;
|
|
|
if ( iHostDataReadConfirmed )
|
if ( iHostDataReadConfirmed )
|
rHostNextState = `HOST_ACK_GEO_REQUEST;
|
rHostNextState = `HOST_ACK_GEO_REQUEST;
|
else
|
else
|
| Line 644... |
Line 666... |
oMemSelect = `SELECT_GEO_MEM;
|
oMemSelect = `SELECT_GEO_MEM;
|
TGA_O = `TAG_DATA_ADDRESS_TYPE;
|
TGA_O = `TAG_DATA_ADDRESS_TYPE;
|
MST_O = 1;
|
MST_O = 1;
|
rInitialWriteAddress = 0;
|
rInitialWriteAddress = 0;
|
rSetWriteAddr = 0;
|
rSetWriteAddr = 0;
|
rCoreBroadCast = 1;
|
//rCoreBroadCast = 1;
|
|
oCoreSelectMask = `SELECT_ALL_CORES;
|
rIncCoreSelect = 0;
|
rIncCoreSelect = 0;
|
RENDREN_O = `SELECT_ALL_CORES;
|
RENDREN_O = `SELECT_ALL_CORES;
|
rResetVertexCount = 0; //Reset the vertex count to zero
|
rResetVertexCount = 0; //Reset the vertex count to zero
|
GACK_O = 0;
|
GACK_O = 0;
|
//STDONE_O = 1;
|
|
oHostDataAvailable = 0;
|
oHostDataAvailable = 0;
|
|
|
|
|
|
|
if (iGPUCommitedResults)
|
if (iGPUCommitedResults)
|
begin
|
begin
|
|
`ifndef VERILATOR
|
`ifndef NO_DISPLAY_STATS
|
`ifndef NO_DISPLAY_STATS
|
for (i = 0; i < `MAX_CORES; i = i + 1)
|
for (i = 0; i < `MAX_CORES; i = i + 1)
|
begin
|
begin
|
$write(".");$fflush;
|
$write(".");
|
|
`ifndef VERILATOR
|
|
$fflush;
|
|
`endif
|
end
|
end
|
|
|
RenderedPixels = RenderedPixels + `MAX_CORES;
|
RenderedPixels = RenderedPixels + `MAX_CORES;
|
if ( RenderedPixels % iDebugWidth == 0)
|
if ( RenderedPixels % iDebugWidth == 0)
|
$write("]%d\n[",RenderedPixels / iDebugWidth);$fflush;
|
$write("]%d\n[",RenderedPixels / iDebugWidth);
|
|
`ifndef VERILATOR
|
|
$fflush;
|
|
`endif
|
|
`endif
|
`endif
|
`endif
|
|
|
rHostNextState = `HOST_PREPARE_FOR_GEO_REQUESTS;
|
rHostNextState = `HOST_PREPARE_FOR_GEO_REQUESTS;
|
end
|
end
|
else
|
else
|
| Line 684... |
Line 714... |
oMemSelect = 0;
|
oMemSelect = 0;
|
TGA_O = 0;
|
TGA_O = 0;
|
MST_O = 0;
|
MST_O = 0;
|
rInitialWriteAddress = 0;
|
rInitialWriteAddress = 0;
|
rSetWriteAddr = 0;
|
rSetWriteAddr = 0;
|
rCoreBroadCast = 0;
|
//rCoreBroadCast = 0;
|
|
oCoreSelectMask = wCoreSelect;
|
rIncCoreSelect = 0;
|
rIncCoreSelect = 0;
|
RENDREN_O = 0;
|
RENDREN_O = 0;
|
rResetVertexCount = 0;
|
rResetVertexCount = 0;
|
GACK_O = 0;
|
GACK_O = 0;
|
//STDONE_O = 0;
|
|
oHostDataAvailable = 0;
|
oHostDataAvailable = 0;
|
|
|
rHostNextState = `HOST_GPU_EXECUTION_DONE;
|
rHostNextState = `HOST_GPU_EXECUTION_DONE;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
| Line 706... |
Line 736... |
oMemSelect = 0;
|
oMemSelect = 0;
|
TGA_O = 0;
|
TGA_O = 0;
|
MST_O = 0;
|
MST_O = 0;
|
rInitialWriteAddress = 0;
|
rInitialWriteAddress = 0;
|
rSetWriteAddr = 0;
|
rSetWriteAddr = 0;
|
rCoreBroadCast = 0;
|
//rCoreBroadCast = 0;
|
|
oCoreSelectMask = wCoreSelect;
|
rIncCoreSelect = 0;
|
rIncCoreSelect = 0;
|
RENDREN_O = 0;
|
RENDREN_O = 0;
|
rResetVertexCount = 0;
|
rResetVertexCount = 0;
|
GACK_O = 0;
|
GACK_O = 0;
|
//STDONE_O = 0;
|
|
oHostDataAvailable = 0;
|
oHostDataAvailable = 0;
|
|
|
rHostNextState = `HOST_IDLE;
|
rHostNextState = `HOST_IDLE;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
