| Line 36... |
Line 36... |
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`define MAX_VERTEX_IN_FRAME `WIDTH'd7 // WAS 8'd6
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`define MAX_VERTEX_IN_FRAME `WIDTH'd7 // WAS 8'd6
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`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01
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`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01
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`define TAG_DATA_ADDRESS_TYPE 2'b10
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`define TAG_DATA_ADDRESS_TYPE 2'b10
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`define SELECT_INST_MEM 3'b00
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`define SELECT_INST_MEM 2'b00
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`define SELECT_SCENE_MEM 3'b01
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`define SELECT_SCENE_MEM 2'b01
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`define SELECT_GEO_MEM 3'b10
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`define SELECT_GEO_MEM 2'b10
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`define HOST_IDLE 0
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`define HOST_IDLE 0
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`define HOST_WRITE_INSTRUCTION 1
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`define HOST_WRITE_INSTRUCTION 1
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`define HOST_WAIT_INSTRUCTION 2
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`define HOST_WAIT_INSTRUCTION 2
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| Line 211... |
Line 211... |
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reg [63:0] i;
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reg [63:0] i;
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reg [63:0] RenderedPixels;
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reg [63:0] RenderedPixels;
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wire wLastVertexInFrame;
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wire wLastVertexInFrame;
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assign wLastVertexInFrame =
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assign wLastVertexInFrame =
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(wVertexCount % `MAX_VERTEX_IN_FRAME == 1'b0 ) ? 1'b1 : 1'b0;
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(wVertexCount % `MAX_VERTEX_IN_FRAME == 32'b0 ) ? 1'b1 : 1'b0;
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reg [31:0] StartTime;
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reg [63:0] StartTime;
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// Host Finite State Machine //
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// Host Finite State Machine //
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always @( * )
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always @( * )
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begin
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begin
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| Line 374... |
Line 374... |
oMemSelect = `SELECT_SCENE_MEM;
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oMemSelect = `SELECT_SCENE_MEM;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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MST_O = 1;
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MST_O = 1;
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rInitialWriteAddress = 0;
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rInitialWriteAddress = 0;
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rSetWriteAddr = 0;
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rSetWriteAddr = 0;
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//rCoreBroadCast = 1;
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oCoreSelectMask = `SELECT_ALL_CORES;
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oCoreSelectMask = `SELECT_ALL_CORES;
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rIncCoreSelect = 0;
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rIncCoreSelect = 0;
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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| Line 404... |
Line 403... |
rInitiaReadAddr = 0;
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rInitiaReadAddr = 0;
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rWBMReset = 0;
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rWBMReset = 0;
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oMemSelect = `SELECT_SCENE_MEM; //We are reading from the scene memory
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oMemSelect = `SELECT_SCENE_MEM; //We are reading from the scene memory
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TGA_O = `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
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TGA_O = `TAG_DATA_ADDRESS_TYPE; //We will write to the DATA section of the core MEM
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MST_O = 1; //Keep master signal in 1 for now
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MST_O = 1; //Keep master signal in 1 for now
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rInitialWriteAddress = `CREG_PIXEL_2D_INITIAL_POSITION; //The address from which to start wrting @ the cores
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rInitialWriteAddress = {16'b0,`CREG_PIXEL_2D_INITIAL_POSITION}; //The address from which to start wrting @ the cores
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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//rCoreBroadCast = 0; //Set to zero to unicast, starting from core 0
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oCoreSelectMask = wCoreSelect;
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oCoreSelectMask = wCoreSelect;
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rIncCoreSelect = 0; //Set to unicast to the next core
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rIncCoreSelect = 0; //Set to unicast to the next core
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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| Line 459... |
Line 457... |
rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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oHostDataAvailable = 0;
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oHostDataAvailable = 0;
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if (wWBMDone && !(oReadAddress % 2))
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if (wWBMDone && ((oReadAddress % 2) == `WB_WIDTH'b0))
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rHostNextState = `HOST_UNICAST_CORE_CONFIG;
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rHostNextState = `HOST_UNICAST_CORE_CONFIG;
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else if (wWBMDone && (oReadAddress % 2) )
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else if (wWBMDone && ((oReadAddress % 2) != `WB_WIDTH'b0))
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rHostNextState = `HOST_PREPARE_NEXT_CORE_CONFIG;
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rHostNextState = `HOST_PREPARE_NEXT_CORE_CONFIG;
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else
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else
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rHostNextState = `HOST_WAIT_CORE_CONFIG;
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rHostNextState = `HOST_WAIT_CORE_CONFIG;
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end
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end
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| Line 480... |
Line 478... |
rInitiaReadAddr = 0;
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rInitiaReadAddr = 0;
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rWBMReset = 0;
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rWBMReset = 0;
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oMemSelect = `SELECT_GEO_MEM;
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oMemSelect = `SELECT_GEO_MEM;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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MST_O = 0; //The master signal goes to zero until request
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MST_O = 0; //The master signal goes to zero until request
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rInitialWriteAddress = `CREG_PIXEL_2D_INITIAL_POSITION; //Write starting from this location on the cores
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rInitialWriteAddress = {16'b0,`CREG_PIXEL_2D_INITIAL_POSITION}; //Write starting from this location on the cores
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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//rCoreBroadCast = 0;
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oCoreSelectMask = wCoreSelect;
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oCoreSelectMask = wCoreSelect;
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rIncCoreSelect = 1; //Moving to configure the next core now
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rIncCoreSelect = 1; //Moving to configure the next core now
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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| Line 508... |
Line 505... |
rInitiaReadAddr = 32'hA; //Start reading from addr 0 @ GEO MEM
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rInitiaReadAddr = 32'hA; //Start reading from addr 0 @ GEO MEM
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rWBMReset = 1; //Tell WBM to start reading from the addr bellow
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rWBMReset = 1; //Tell WBM to start reading from the addr bellow
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oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
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oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
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TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
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TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
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MST_O = 0; //The master signal goes to zero until request
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MST_O = 0; //The master signal goes to zero until request
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rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores
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rInitialWriteAddress = {16'b0,`CREG_V0}; //Write starting from this location on the cores
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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//rCoreBroadCast = 1; //From now on we only broadcast
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oCoreSelectMask = `SELECT_ALL_CORES;
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oCoreSelectMask = `SELECT_ALL_CORES;
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rIncCoreSelect = 0; //Ignored during broadcasts
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rIncCoreSelect = 0; //Ignored during broadcasts
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 1;
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rResetVertexCount = 1;
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GACK_O = 0;
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GACK_O = 0;
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| Line 533... |
Line 529... |
rInitiaReadAddr = 0; //Ignored
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rInitiaReadAddr = 0; //Ignored
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rWBMReset = 0; //Ignored
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rWBMReset = 0; //Ignored
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oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
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oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
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TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
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TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
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MST_O = 0; //The master signal goes to zero until request
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MST_O = 0; //The master signal goes to zero until request
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rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores
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rInitialWriteAddress = {16'b0,`CREG_V0}; //Write starting from this location on the cores
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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//rCoreBroadCast = 1; //From now on we only broadcast
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oCoreSelectMask = `SELECT_ALL_CORES;
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oCoreSelectMask = `SELECT_ALL_CORES;
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rIncCoreSelect = 0; //Ignored during broadcasts
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rIncCoreSelect = 0; //Ignored during broadcasts
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 1;
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GACK_O = 1;
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| Line 612... |
Line 607... |
oMemSelect = `SELECT_GEO_MEM;
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oMemSelect = `SELECT_GEO_MEM;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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MST_O = 1; //Start the Transmition
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MST_O = 1; //Start the Transmition
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rInitialWriteAddress = 0;
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rInitialWriteAddress = 0;
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rSetWriteAddr = 0;
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rSetWriteAddr = 0;
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//rCoreBroadCast = 1;
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oCoreSelectMask = `SELECT_ALL_CORES;
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oCoreSelectMask = `SELECT_ALL_CORES;
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rIncCoreSelect = 0;
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rIncCoreSelect = 0;
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RENDREN_O = `SELECT_ALL_CORES;
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RENDREN_O = `SELECT_ALL_CORES;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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| Line 640... |
Line 634... |
rInitiaReadAddr = 0; //Ignored
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rInitiaReadAddr = 0; //Ignored
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rWBMReset = 0; //Continue from previous read address
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rWBMReset = 0; //Continue from previous read address
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oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
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oMemSelect = `SELECT_GEO_MEM; //Use external GEO mem for reading
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TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
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TGA_O = `TAG_DATA_ADDRESS_TYPE; //We write to the data MEM @ the cores
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MST_O = 0; //The master signal goes to zero until request
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MST_O = 0; //The master signal goes to zero until request
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rInitialWriteAddress = `CREG_V0; //Write starting from this location on the cores
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rInitialWriteAddress = {16'b0,`CREG_V0}; //Write starting from this location on the cores
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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rSetWriteAddr = 1; //Set to use the initial write address bellow
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//rCoreBroadCast = 1; //From now on we only broadcast
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oCoreSelectMask = `SELECT_ALL_CORES;
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oCoreSelectMask = `SELECT_ALL_CORES;
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rIncCoreSelect = 0; //Ignored during broadcasts
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rIncCoreSelect = 0; //Ignored during broadcasts
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RENDREN_O = `SELECT_ALL_CORES;
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RENDREN_O = `SELECT_ALL_CORES;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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| Line 666... |
Line 659... |
oMemSelect = `SELECT_GEO_MEM;
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oMemSelect = `SELECT_GEO_MEM;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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TGA_O = `TAG_DATA_ADDRESS_TYPE;
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MST_O = 1;
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MST_O = 1;
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rInitialWriteAddress = 0;
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rInitialWriteAddress = 0;
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rSetWriteAddr = 0;
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rSetWriteAddr = 0;
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//rCoreBroadCast = 1;
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oCoreSelectMask = `SELECT_ALL_CORES;
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oCoreSelectMask = `SELECT_ALL_CORES;
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rIncCoreSelect = 0;
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rIncCoreSelect = 0;
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RENDREN_O = `SELECT_ALL_CORES;
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RENDREN_O = `SELECT_ALL_CORES;
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rResetVertexCount = 0; //Reset the vertex count to zero
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rResetVertexCount = 0; //Reset the vertex count to zero
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GACK_O = 0;
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GACK_O = 0;
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| Line 705... |
Line 697... |
rHostNextState = `HOST_LAST_PRIMITIVE_REACHED;
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rHostNextState = `HOST_LAST_PRIMITIVE_REACHED;
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end
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end
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//----------------------------------------
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//----------------------------------------
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`HOST_GPU_EXECUTION_DONE:
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`HOST_GPU_EXECUTION_DONE:
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begin
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begin
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$display("THEIA Execution done in %dns\n",$time-StartTime);
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$display("THEIA Execution done in %xns\n",$time-StartTime);
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rWBMEnable = 0;
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rWBMEnable = 0;
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rInitiaReadAddr = 0;
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rInitiaReadAddr = 0;
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rWBMReset = 0;
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rWBMReset = 0;
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oMemSelect = 0;
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oMemSelect = 0;
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TGA_O = 0;
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TGA_O = 0;
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MST_O = 0;
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MST_O = 0;
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rInitialWriteAddress = 0;
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rInitialWriteAddress = 0;
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rSetWriteAddr = 0;
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rSetWriteAddr = 0;
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//rCoreBroadCast = 0;
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oCoreSelectMask = wCoreSelect;
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oCoreSelectMask = wCoreSelect;
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rIncCoreSelect = 0;
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rIncCoreSelect = 0;
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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| Line 736... |
Line 727... |
oMemSelect = 0;
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oMemSelect = 0;
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TGA_O = 0;
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TGA_O = 0;
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MST_O = 0;
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MST_O = 0;
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rInitialWriteAddress = 0;
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rInitialWriteAddress = 0;
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rSetWriteAddr = 0;
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rSetWriteAddr = 0;
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//rCoreBroadCast = 0;
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oCoreSelectMask = wCoreSelect;
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oCoreSelectMask = wCoreSelect;
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rIncCoreSelect = 0;
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rIncCoreSelect = 0;
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RENDREN_O = 0;
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RENDREN_O = 0;
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rResetVertexCount = 0;
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rResetVertexCount = 0;
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GACK_O = 0;
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GACK_O = 0;
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