URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [icarus_version/] [rtl/] [Module_RAM.v] - Diff between revs 166 and 175

Rev 166	Rev 175
Line 33...	Line 33...
`input wire[DATA_WIDTH-1:0] iDataIn,`	`input wire[DATA_WIDTH-1:0] iDataIn,`
`output reg [DATA_WIDTH-1:0] oDataOut0,`	`output reg [DATA_WIDTH-1:0] oDataOut0,`
`output reg [DATA_WIDTH-1:0] oDataOut1`	`output reg [DATA_WIDTH-1:0] oDataOut1`
`);`	`);`

`reg [DATA_WIDTH-1:0] Ram [MEM_SIZE:0];`	`reg [DATA_WIDTH-1:0] Ram [MEM_SIZE-1:0];`

`always @(posedge Clock)`	`always @(posedge Clock)`
`begin`	`begin`

	`/* verilator lint_off WIDTH */`
`if (iWriteEnable)`	`if (iWriteEnable)`
`Ram[iWriteAddress] <= iDataIn;`	`Ram[iWriteAddress] <= iDataIn;`


`oDataOut0 <= Ram[iReadAddress0];`	`oDataOut0 <= Ram[iReadAddress0];`
`oDataOut1 <= Ram[iReadAddress1];`	`oDataOut1 <= Ram[iReadAddress1];`
	`/* verilator lint_on WIDTH */`

`end`	`end`
`endmodule`	`endmodule`
`//--------------------------------------------------------`	`//--------------------------------------------------------`

Line 60...	Line 62...
`input wire[DATA_WIDTH-1:0] iDataIn,`	`input wire[DATA_WIDTH-1:0] iDataIn,`
`output reg [DATA_WIDTH-1:0] oDataOut0`	`output reg [DATA_WIDTH-1:0] oDataOut0`

`);`	`);`

`reg [DATA_WIDTH-1:0] Ram [MEM_SIZE:0];`	`reg [DATA_WIDTH-1:0] Ram [MEM_SIZE-1:0];`

`always @(posedge Clock)`	`always @(posedge Clock)`
`begin`	`begin`

`if (iWriteEnable)`	`if (iWriteEnable)`