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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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`ifdef VERILATOR
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`include "Module_Swizzle.v"
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`include "Module_ArithmeticComparison.v"
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`include "Module_RadixRMul.v"
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`include "Module_FixedPointDivision.v"
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`include "Module_FixedPointSquareRoot.v"
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`endif
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/**********************************************************************************
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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This program is free software; you can redistribute it and/or
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assign IOW_Operation = (iOperation == `OMWRITE);
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assign IOW_Operation = (iOperation == `OMWRITE);
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always @ ( * )
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always @ ( * )
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begin
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begin
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if (iOperation == `RET)
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if (iOperation == `RET)
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oReturnFromSub <= OutputReady;
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oReturnFromSub = OutputReady;
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else
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else
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oReturnFromSub <= 1'b0;
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oReturnFromSub = 1'b0;
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end
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end
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1_AWE
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1_AWE
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(
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(
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Line 1108... |
endcase
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endcase
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end
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end
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//------------------------------------------------------------------------
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//------------------------------------------------------------------------
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//Output ready logic Stuff for Division...
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//Output ready logic Stuff for Division...
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//Some FFT will hopefully do the trick
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//Some FFT will hopefully do the trick
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/* verilator lint_off UNOPTFLAT*/
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wire wDivisionOutputReadyA,wDivisionOutputReadyB,wDivisionOutputReadyC;
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wire wDivisionOutputReadyA,wDivisionOutputReadyB,wDivisionOutputReadyC;
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wire wDivisionOutputReady;
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wire wDivisionOutputReady;
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/* verilator lint_on UNOPTFLAT*/
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assign wAddSubAOutputReady = wAddSubA_OutputReady;
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assign wAddSubAOutputReady = wAddSubA_OutputReady;
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assign wAddSubBOutputReady = wAddSubB_OutputReady;
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assign wAddSubBOutputReady = wAddSubB_OutputReady;
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assign wAddSubCOutputReady = wAddSubC_OutputReady;
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assign wAddSubCOutputReady = wAddSubC_OutputReady;
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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//------------------------------------------------------------------------
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//------------------------------------------------------------------------
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