| Line 57... |
Line 57... |
//Connections to the R Memory
|
//Connections to the R Memory
|
output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadAddress,
|
output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadAddress,
|
input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadData,
|
input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadData,
|
input wire iTMEMDataAvailable,
|
input wire iTMEMDataAvailable,
|
output wire oTMEMDataRequest,
|
output wire oTMEMDataRequest,
|
|
|
output reg OutputReady
|
output reg OutputReady
|
|
|
);
|
);
|
|
|
|
|
| Line 828... |
Line 827... |
`DEC: wAddSubB_By = (`LONG_WIDTH'd1 << `SCALE);
|
`DEC: wAddSubB_By = (`LONG_WIDTH'd1 << `SCALE);
|
`MOD: wAddSubB_By = (`LONG_WIDTH'd1 << `SCALE);
|
`MOD: wAddSubB_By = (`LONG_WIDTH'd1 << `SCALE);
|
`MAG: wAddSubB_By = wMultiplicationC_Result; //C^2
|
`MAG: wAddSubB_By = wMultiplicationC_Result; //C^2
|
`DOT: wAddSubB_By = wMultiplicationC_Result; //Az * Bz
|
`DOT: wAddSubB_By = wMultiplicationC_Result; //Az * Bz
|
`CROSS: wAddSubB_By = wMultiplicationD_Result;
|
`CROSS: wAddSubB_By = wMultiplicationD_Result;
|
default: wAddSubB_By = 32'b0;
|
default: wAddSubB_By = `LONG_WIDTH'b0;
|
endcase
|
endcase
|
end
|
end
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
wire [`LONG_WIDTH-1:0] wAddSubC_Result;
|
wire [`LONG_WIDTH-1:0] wAddSubC_Result;
|
reg [`LONG_WIDTH-1:0] wAddSubC_Az,wAddSubC_Bz;
|
reg [`LONG_WIDTH-1:0] wAddSubC_Az,wAddSubC_Bz;
|
| Line 911... |
Line 910... |
.OutputReady( wSquareRoot_OutputReady ),
|
.OutputReady( wSquareRoot_OutputReady ),
|
.Result( wSquareRoot_Result )
|
.Result( wSquareRoot_Result )
|
);
|
);
|
//------------------------------------------------------
|
//------------------------------------------------------
|
|
|
assign wModulus2N_ResultA = (iChannel_Ax & wAddSubA_Result );
|
assign wModulus2N_ResultA = ({32'b0,iChannel_Ax} & wAddSubA_Result );
|
assign wModulus2N_ResultB = (iChannel_Ay & wAddSubB_Result );
|
assign wModulus2N_ResultB = ({32'b0,iChannel_Ay} & wAddSubB_Result );
|
assign wModulus2N_ResultC = (iChannel_Az & wAddSubC_Result );
|
assign wModulus2N_ResultC = ({32'b0,iChannel_Az} & wAddSubC_Result );
|
|
|
|
|
|
|
|
|
|
|
| Line 951... |
Line 950... |
`SETX,`RET: ResultA = iChannel_Ax;
|
`SETX,`RET: ResultA = iChannel_Ax;
|
`SETY: ResultA = iChannel_Bx;
|
`SETY: ResultA = iChannel_Bx;
|
`SETZ: ResultA = iChannel_Bx;
|
`SETZ: ResultA = iChannel_Bx;
|
`INC,`INCX,`INCY,`INCZ: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};
|
`INC,`INCX,`INCY,`INCZ: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};
|
`DEC: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};
|
`DEC: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};
|
`MOD: ResultA = wModulus2N_ResultA;
|
`MOD: ResultA = wModulus2N_ResultA[31:0];
|
`FRAC: ResultA = iChannel_Ax & (`WIDTH'hFFFFFFFF >> (`WIDTH - `SCALE));
|
`FRAC: ResultA = iChannel_Ax & (`WIDTH'hFFFFFFFF >> (`WIDTH - `SCALE));
|
`MULP: ResultA = iChannel_Ax;
|
`MULP: ResultA = iChannel_Ax;
|
`NEG: ResultA = ~iChannel_Ax + 1'b1;
|
`NEG: ResultA = ~iChannel_Ax + 1'b1;
|
`XCHANGEX: ResultA = iChannel_Bx;
|
`XCHANGEX: ResultA = iChannel_Bx;
|
|
|
| Line 996... |
Line 995... |
|
|
`SWIZZLE3D: ResultB = wSwizzleOutputY;
|
`SWIZZLE3D: ResultB = wSwizzleOutputY;
|
|
|
`INC,`INCX,`INCY,`INCZ: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; // & 32'h7FFFFFFF;
|
`INC,`INCX,`INCY,`INCZ: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; // & 32'h7FFFFFFF;
|
`DEC: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; // & 32'h7FFFFFFF;
|
`DEC: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]}; // & 32'h7FFFFFFF;
|
`MOD: ResultB = wModulus2N_ResultB;
|
`MOD: ResultB = wModulus2N_ResultB[31:0];
|
`FRAC: ResultB = iChannel_Ay & (`WIDTH'hFFFFFFFF >> (`WIDTH - `SCALE));
|
`FRAC: ResultB = iChannel_Ay & (`WIDTH'hFFFFFFFF >> (`WIDTH - `SCALE));
|
`MULP: ResultB = iChannel_Ay;
|
`MULP: ResultB = iChannel_Ay;
|
`NEG: ResultB = ~iChannel_Ay + 1'b1;
|
`NEG: ResultB = ~iChannel_Ay + 1'b1;
|
`XCHANGEX: ResultB = iChannel_Ay;
|
`XCHANGEX: ResultB = iChannel_Ay;
|
|
|
| Line 1041... |
Line 1040... |
`SETY: ResultC = iChannel_Bz; // {Source0[95:64],Source1[95:64],Source0[31:0]};
|
`SETY: ResultC = iChannel_Bz; // {Source0[95:64],Source1[95:64],Source0[31:0]};
|
`SETZ: ResultC = iChannel_Ax; // {Source0[95:64],Source0[63:32],Source1[95:64]};
|
`SETZ: ResultC = iChannel_Ax; // {Source0[95:64],Source0[63:32],Source1[95:64]};
|
|
|
`INC,`INCX,`INCY,`INCZ: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF;
|
`INC,`INCX,`INCY,`INCZ: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF;
|
`DEC: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF;
|
`DEC: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF;
|
`MOD: ResultC = wModulus2N_ResultC;
|
`MOD: ResultC = wModulus2N_ResultC[31:0];
|
`FRAC: ResultC = iChannel_Az & (`WIDTH'hFFFFFFFF >> (`WIDTH - `SCALE));
|
`FRAC: ResultC = iChannel_Az & (`WIDTH'hFFFFFFFF >> (`WIDTH - `SCALE));
|
`MULP: ResultC = wMultiplicationA_Result[31:0];
|
`MULP: ResultC = wMultiplicationA_Result[31:0];
|
`NEG: ResultC = ~iChannel_Az + 1'b1;
|
`NEG: ResultC = ~iChannel_Az + 1'b1;
|
`XCHANGEX: ResultC = iChannel_Az;
|
`XCHANGEX: ResultC = iChannel_Az;
|
default:
|
default:
|
| Line 1108... |
Line 1107... |
endcase
|
endcase
|
end
|
end
|
//------------------------------------------------------------------------
|
//------------------------------------------------------------------------
|
//Output ready logic Stuff for Division...
|
//Output ready logic Stuff for Division...
|
//Some FFT will hopefully do the trick
|
//Some FFT will hopefully do the trick
|
/* verilator lint_off UNOPTFLAT*/
|
|
wire wDivisionOutputReadyA,wDivisionOutputReadyB,wDivisionOutputReadyC ;
|
wire wDivisionOutputReadyA,wDivisionOutputReadyB,wDivisionOutputReadyC ;
|
wire wDivisionOutputReady;
|
wire wDivisionOutputReady;
|
/* verilator lint_on UNOPTFLAT*/
|
|
|
|
|
|
assign wAddSubAOutputReady = wAddSubA_OutputReady;
|
assign wAddSubAOutputReady = wAddSubA_OutputReady;
|
assign wAddSubBOutputReady = wAddSubB_OutputReady;
|
assign wAddSubBOutputReady = wAddSubB_OutputReady;
|
assign wAddSubCOutputReady = wAddSubC_OutputReady;
|
assign wAddSubCOutputReady = wAddSubC_OutputReady;
|
|
|
|
wire wDivA_tmp, wDivB_tmp, wDivC_tmp;
|
FFT1 FFT_DivisionA
|
UPCOUNTER_POSEDGE # (1) FFT_DivisionA
|
(
|
(
|
.D(1'b1),
|
.Clock(Clock),
|
.Clock( wDivisionA_OutputReady ),
|
.Reset(Reset | iInputReady),
|
.Reset( iInputReady ),
|
.Initial(1'b0),
|
.Q( wDivisionOutputReadyA )
|
.Enable(wDivisionA_OutputReady),
|
|
.Q(wDivA_tmp)
|
);
|
);
|
|
|
FFT1 FFT_DivisionB
|
assign wDivisionOutputReadyA = ((wDivA_tmp | wDivisionA_OutputReady) & ~iInputReady);
|
|
UPCOUNTER_POSEDGE # (1) FFT_DivisionB
|
(
|
(
|
.D(1'b1),
|
.Clock(Clock),
|
.Clock( wDivisionB_OutputReady ),
|
.Reset(Reset | iInputReady),
|
.Reset( iInputReady ),
|
.Initial(1'b0),
|
.Q( wDivisionOutputReadyB )
|
.Enable(wDivisionB_OutputReady),
|
|
.Q(wDivB_tmp)
|
);
|
);
|
|
assign wDivisionOutputReadyB = ((wDivB_tmp | wDivisionB_OutputReady) & ~iInputReady);
|
|
|
FFT1 FFT_DivisionC
|
UPCOUNTER_POSEDGE # (1) FFT_DivisionC
|
(
|
(
|
.D(1'b1),
|
.Clock(Clock),
|
.Clock( wDivisionC_OutputReady ),
|
.Reset(Reset | iInputReady),
|
.Reset( iInputReady ),
|
.Initial(1'b0),
|
.Q( wDivisionOutputReadyC )
|
.Enable(wDivisionC_OutputReady),
|
|
.Q(wDivC_tmp)
|
);
|
);
|
|
assign wDivisionOutputReadyC = ((wDivC_tmp | wDivisionC_OutputReady) & ~iInputReady);
|
|
/*
|
|
FFT1 FFT_DivisionA
|
|
(
|
|
.D(1'b1),
|
|
.Clock( wDivisionA_OutputReady ),
|
|
.Reset( iInputReady ),
|
|
.Q( wDivisionOutputReadyA )
|
|
);
|
|
|
|
FFT1 FFT_DivisionB
|
|
(
|
|
.D(1'b1),
|
|
.Clock( wDivisionB_OutputReady ),
|
|
.Reset( iInputReady ),
|
|
.Q( wDivisionOutputReadyB )
|
|
);
|
|
|
|
FFT1 FFT_DivisionC
|
|
(
|
|
.D(1'b1),
|
|
.Clock( wDivisionC_OutputReady ),
|
|
.Reset( iInputReady ),
|
|
.Q( wDivisionOutputReadyC )
|
|
);
|
|
*/
|
assign wDivisionOutputReady =
|
assign wDivisionOutputReady =
|
( wDivisionOutputReadyA && wDivisionOutputReadyB && wDivisionOutputReadyC );
|
( wDivisionOutputReadyA && wDivisionOutputReadyB && wDivisionOutputReadyC );
|
|
|
assign wMultiplicationOutputReadyA = wMultiplicationA_OutputReady;
|
assign wMultiplicationOutputReadyA = wMultiplicationA_OutputReady;
|
assign wMultiplicationOutputReadyB = wMultiplicationB_OutputReady;
|
assign wMultiplicationOutputReadyB = wMultiplicationB_OutputReady;
|
| Line 1274... |
Line 1303... |
`XCHANGEX: OutputReady = wOutputDelay1Cycle;
|
`XCHANGEX: OutputReady = wOutputDelay1Cycle;
|
|
|
|
|
default:
|
default:
|
begin
|
begin
|
OutputReady = 32'b0;
|
OutputReady = 1'b0;
|
//`ifdef DEBUG
|
//`ifdef DEBUG
|
//$display("*** ALU ERROR: iOperation = %d ***",iOperation);
|
//$display("*** ALU ERROR: iOperation = %d ***",iOperation);
|
//`endif
|
//`endif
|
end
|
end
|
|
|
