| Line 106... |
Line 106... |
wire [`MAX_CORES-1:0] wTMEM_Resquest;
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wire [`MAX_CORES-1:0] wTMEM_Resquest;
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wire [`MAX_CORES-1:0] wTMEM_Granted;
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wire [`MAX_CORES-1:0] wTMEM_Granted;
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//CROSS-BAR cables
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//CROSS-BAR wires
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wire [`WB_WIDTH-1:0] wCrossBarDataRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank
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wire [`WB_WIDTH-1:0] wCrossBarDataRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank
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wire [`WB_WIDTH-1:0] wCrossBarDataCollumn[`MAX_CORES-1:0]; //Vertical grid buses comming from each core.
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wire [`WB_WIDTH-1:0] wCrossBarDataCollumn[`MAX_CORES-1:0]; //Vertical grid buses comming from each core.
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wire [`WB_WIDTH-1:0] wTMemReadAdr[`MAX_CORES-1:0]; //Horizontal grid Buses comming from each core (virtual addr).
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wire [`WB_WIDTH-1:0] wTMemReadAdr[`MAX_CORES-1:0]; //Horizontal grid Buses comming from each core (virtual addr).
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wire [`WB_WIDTH-1:0] wCrossBarAdressCollumn[`MAX_CORES-1:0]; //Vertical grid buses comming from each core. (physical addr).
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wire [`WB_WIDTH-1:0] wCrossBarAdressCollumn[`MAX_CORES-1:0]; //Vertical grid buses comming from each core. (physical addr).
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wire [`WB_WIDTH-1:0] wCrossBarAddressRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank.
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wire [`WB_WIDTH-1:0] wCrossBarAddressRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank.
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wire wCORE_2_TMEM__Req[`MAX_CORES-1:0];
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wire wCORE_2_TMEM__Req[`MAX_CORES-1:0];
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wire [`MAX_TMEM_BANKS -1:0] wBankReadRequest[`MAX_CORES-1:0];
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wire [`MAX_TMEM_BANKS -1:0] wBankReadRequest[`MAX_CORES-1:0];
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wire [`MAX_CORES-1:0] wBankReadGranted[`MAX_TMEM_BANKS-1:0];
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wire [`MAX_CORES-1:0] wBankReadGranted[`MAX_TMEM_BANKS-1:0];
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wire wTMEM_2_Core__Grant[`MAX_CORES-1:0];
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wire wTMEM_2_Core__Grant[`MAX_CORES-1:0];
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wire[`MAX_CORE_BITS-1:0] wCurrentCoreSelected[`MAX_TMEM_BANKS-1:0];
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wire[`MAX_CORE_BITS-1:0] wCurrentCoreSelected[`MAX_TMEM_BANKS-1:0];
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wire[`WIDTH-1:0] wCoreBankSelect[`MAX_CORES-1:0];
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wire[`WIDTH-1:0] wCoreBankSelect[`MAX_CORES-1:0];
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wire [`MAX_CORES-1:0] wHDL_O;
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wire [`MAX_CORES-1:0] wHDL_O;
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wire [`MAX_CORES-1:0] wHostDataLatched;
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wire [`MAX_CORES-1:0] wHostDataLatched;
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wire [`MAX_CORES-1:0] wRCOMMIT_O;
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wire [`MAX_CORES-1:0] wRCOMMIT_O;
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wire [`MAX_CORES-1:0] wRCommited;
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wire [`MAX_CORES-1:0] wRCommited;
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Line 147... |
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);
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);
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//----------------------------------------------------------------
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//----------------------------------------------------------------
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wire wMaskedACK_O;
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wire wMaskedACK_O;
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assign wMaskedACK_O = (SEL_I & wACK_O) ? 1'b1 : 1'b0;
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assign wMaskedACK_O = ( (SEL_I & wACK_O) != `MAX_CORES'b0) ? 1'b1 : 1'b0;
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assign ACK_O = ( MST_I ) ? wMaskedACK_O : wACK_O[ wBusSelect];
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assign ACK_O = ( MST_I ) ? wMaskedACK_O : wACK_O[ wBusSelect];
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wire [`WB_WIDTH-1:0] wDataOut[`MAX_CORES-1:0];
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wire [`WB_WIDTH-1:0] wDataOut[`MAX_CORES-1:0];
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assign OMEM_O = wDataOut[ OMBSEL_I ];
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assign OMEM_O = wDataOut[ OMBSEL_I ];
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