| Line 110... |
Line 110... |
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//CROSS-BAR wires
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//CROSS-BAR wires
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wire [`WB_WIDTH-1:0] wCrossBarDataRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank
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wire [(`MAX_TMEM_BANKS*`WB_WIDTH)-1:0] wCrossBarDataRow; //Horizontal grid Buses comming from each bank
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wire [`WB_WIDTH-1:0] wCrossBarDataCollumn[`MAX_CORES-1:0]; //Vertical grid buses comming from each core.
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wire [(`MAX_CORES*`WB_WIDTH)-1:0] wCrossBarDataCollumn; //Vertical grid buses comming from each core.
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wire [(`MAX_CORES*`WB_WIDTH)-1:0] wCrossBarAdressCollumn; //Vertical grid buses comming from each core. (physical addr).
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wire [`WB_WIDTH-1:0] wTMemReadAdr[`MAX_CORES-1:0]; //Horizontal grid Buses comming from each core (virtual addr).
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wire [`WB_WIDTH-1:0] wTMemReadAdr[`MAX_CORES-1:0]; //Horizontal grid Buses comming from each core (virtual addr).
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wire [`WB_WIDTH-1:0] wCrossBarAdressCollumn[`MAX_CORES-1:0]; //Vertical grid buses comming from each core. (physical addr).
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wire [`WB_WIDTH-1:0] wCrossBarAddressRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank.
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wire [`WB_WIDTH-1:0] wCrossBarAddressRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank.
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wire wCORE_2_TMEM__Req[`MAX_CORES-1:0];
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wire wCORE_2_TMEM__Req[`MAX_CORES-1:0];
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wire [`MAX_TMEM_BANKS -1:0] wBankReadRequest[`MAX_CORES-1:0];
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wire [`MAX_TMEM_BANKS -1:0] wBankReadRequest[`MAX_CORES-1:0];
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wire [`MAX_CORES-1:0] wBankReadGranted[`MAX_TMEM_BANKS-1:0];
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wire [`MAX_CORES-1:0] wBankReadGranted[`MAX_TMEM_BANKS-1:0];
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wire wTMEM_2_Core__Grant[`MAX_CORES-1:0];
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wire wTMEM_2_Core__Grant[`MAX_CORES-1:0];
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| Line 192... |
Line 193... |
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.OMEM_WE_O( wOMem_WE[i] ),
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.OMEM_WE_O( wOMem_WE[i] ),
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.OMEM_ADR_O( wOMEM_Address[i] ),
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.OMEM_ADR_O( wOMEM_Address[i] ),
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.OMEM_DAT_O( wOMEM_Dat[i] ),
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.OMEM_DAT_O( wOMEM_Dat[i] ),
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.TMEM_DAT_I( wCrossBarDataCollumn[i] ),
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.TMEM_DAT_I( wCrossBarDataCollumn[ (i*`WB_WIDTH)+:`WB_WIDTH ] ),
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.TMEM_ADR_O( wTMemReadAdr[i] ),
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.TMEM_ADR_O( wTMemReadAdr[i] ),
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.TMEM_CYC_O( wCORE_2_TMEM__Req[i] ),
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.TMEM_CYC_O( wCORE_2_TMEM__Req[i] ),
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.TMEM_GNT_I( wTMEM_2_Core__Grant[i] ),
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.TMEM_GNT_I( wTMEM_2_Core__Grant[i] ),
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.HDA_I( HDA_I ), //Host data available
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.HDA_I( HDA_I ), //Host data available
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| Line 240... |
Line 241... |
.oDataOut0( wDataOut[i] )
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.oDataOut0( wDataOut[i] )
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);
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);
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MUXFULLPARALELL_GENERIC # (`WB_WIDTH,`MAX_TMEM_BANKS,`MAX_TMEM_BITS) MUXG1
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(
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.in_bus( wCrossBarDataRow ),
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.sel( wCoreBankSelect[ i ][0+:`MAX_TMEM_BITS] ),
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.out( wCrossBarDataCollumn[ (i*`WB_WIDTH)+:`WB_WIDTH ] )
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);
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//If there are "n" banks, memory location "X" would reside in bank number X mod n.
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//If there are "n" banks, memory location "X" would reside in bank number X mod n.
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//X mod 2^n == X & (2^n - 1)
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//X mod 2^n == X & (2^n - 1)
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assign wCoreBankSelect[i] = (wTMemReadAdr[i] & (`MAX_TMEM_BANKS-1));
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assign wCoreBankSelect[i] = (wTMemReadAdr[i] & (`MAX_TMEM_BANKS-1));
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//Each core has 1 bank request slot
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//Each core has 1 bank request slot
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//Each slot has MAX_TMEM_BANKS bits. Only 1 bit can
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//Each slot has MAX_TMEM_BANKS bits. Only 1 bit can
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//be 1 at any given point in time. All bits zero means,
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//be 1 at any given point in time. All bits zero means,
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//we are not requesting to read from any memory bank.
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//we are not requesting to read from any memory bank.
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SELECT_1_TO_N # ( `WIDTH, `MAX_CORES ) READDRQ
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SELECT_1_TO_N # ( `WIDTH, `MAX_TMEM_BANKS ) READDRQ
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(
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(
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.Sel(wCoreBankSelect[ i]),
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.Sel(wCoreBankSelect[ i]),
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.En(wCORE_2_TMEM__Req[i]),
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.En(wCORE_2_TMEM__Req[i]),
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.O(wBankReadRequest[i])
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.O(wBankReadRequest[i])
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);
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);
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| Line 260... |
Line 268... |
//The address coming from the core is virtual adress, meaning it assumes linear
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//The address coming from the core is virtual adress, meaning it assumes linear
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//address space, however, since memory is interleaved in a n-way memory we transform
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//address space, however, since memory is interleaved in a n-way memory we transform
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//virtual adress into physical adress (relative to the bank) like this
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//virtual adress into physical adress (relative to the bank) like this
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//fadr = vadr / n = vadr >> log2(n)
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//fadr = vadr / n = vadr >> log2(n)
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assign wCrossBarAdressCollumn[i] = (wTMemReadAdr[i] >> `MAX_CORE_BITS);
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assign wCrossBarAdressCollumn[(i*`WB_WIDTH)+:`WB_WIDTH] = (wTMemReadAdr[i] >> `MAX_CORE_BITS);
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//Connect the granted signal to Arbiter of the Bank we want to read from
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//Connect the granted signal to Arbiter of the Bank we want to read from
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assign wTMEM_2_Core__Grant[i] = wBankReadGranted[wCoreBankSelect[i]][i];
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assign wTMEM_2_Core__Grant[i] = wBankReadGranted[wCoreBankSelect[i]][i];
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//Connect the request signal to Arbiter of the Bank we want to read from
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//Connect the request signal to Arbiter of the Bank we want to read from
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| Line 280... |
Line 288... |
generate
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generate
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for (Bank = 0; Bank < `MAX_TMEM_BANKS; Bank = Bank + 1)
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for (Bank = 0; Bank < `MAX_TMEM_BANKS; Bank = Bank + 1)
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begin : BANK
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begin : BANK
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//The memory bank itself
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//The memory bank itself
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RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 50000 ) TMEM
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RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 50000 ) TMEM
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(
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(
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.Clock( CLK_I ),
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.Clock( CLK_I ),
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.iWriteEnable( wTMemWriteEnable[Bank] ),
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.iWriteEnable( wTMemWriteEnable[Bank] ),
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.iWriteAddress( TMADR_I ),
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.iWriteAddress( TMADR_I ),
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.iDataIn( TMDAT_I ),
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.iDataIn( TMDAT_I ),
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.iReadAddress0( wCrossBarAddressRow[Bank] ), //Connect to the Row of the grid
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.iReadAddress0( wCrossBarAddressRow[Bank] ), //Connect to the Row of the grid
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.oDataOut0( wCrossBarDataRow[Bank] ) //Connect to the Row of the grid
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.oDataOut0( wCrossBarDataRow[(`WB_WIDTH*Bank)+:`WB_WIDTH] ) //Connect to the Row of the grid
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);
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);
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//Arbiter will Round-Robin Cores attempting to read from the same Bank
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//Arbiter will Round-Robin Cores attempting to read from the same Bank
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//at a given point in time
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//at a given point in time
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| Line 313... |
Line 322... |
.Enable( 1'b1 ),
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.Enable( 1'b1 ),
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.D(wBankReadGrantedDelay[Bank]),
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.D(wBankReadGrantedDelay[Bank]),
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.Q(wBankReadGranted[Bank])
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.Q(wBankReadGranted[Bank])
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);
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);
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MUXFULLPARALELL_GENERIC # (`WB_WIDTH,`MAX_CORES,`MAX_CORE_BITS) MUXG2
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(
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.in_bus( wCrossBarAdressCollumn ),
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.sel( wCurrentCoreSelected[ Bank ] ),
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.out( wCrossBarAddressRow[ Bank ] )
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);
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//Create the Cross-Bar interconnection grid now, rows are coonected to the memory banks,
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//Create the Cross-Bar interconnection grid now, rows are coonected to the memory banks,
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//while collumns are connected to the cores, 2 or more cores can not read from the same
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//while collumns are connected to the cores, 2 or more cores can not read from the same
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//bank at any given point in time
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//bank at any given point in time
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for (Core = 0; Core < `MAX_CORES; Core = Core + 1)
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//for (Core = 0; Core < `MAX_CORES; Core = Core + 1)
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begin: CORE_CONNECT
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//begin: CORE_CONNECT
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`ifndef VERILATOR
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//`ifndef VERILATOR
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//Connect the Data Collum of this core to the Data Row of current bank, only if the Core is looking for data stored in this bank
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//Connect the Data Collum of this core to the Data Row of current bank, only if the Core is looking for data stored in this bank
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assign wCrossBarDataCollumn[ Core ] = ( wCoreBankSelect[ Core ] == Bank ) ? wCrossBarDataRow[ Bank ] : `WB_WIDTH'bz;
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// assign wCrossBarDataCollumn[ Core ] = ( wCoreBankSelect[ Core ] == Bank ) ? wCrossBarDataRow[ Bank ] : `WB_WIDTH'bz;
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//Connect the Address Row of this Bank to the Address Column of the core, only if the Arbiter selected this core for reading
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//Connect the Address Row of this Bank to the Address Column of the core, only if the Arbiter selected this core for reading
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assign wCrossBarAddressRow[ Bank ] = ( wCurrentCoreSelected[ Bank ] == Core ) ? wCrossBarAdressCollumn[Core]: `WB_WIDTH'bz;
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//assign wCrossBarAddressRow[ Bank ] = ( wCurrentCoreSelected[ Bank ] == Core ) ? wCrossBarAdressCollumn[Core]: `WB_WIDTH'bz;
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`endif
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end
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//`endif
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//end
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end
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end
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endgenerate
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endgenerate
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////////////// CROSS-BAR INTERCONECTION//////////////////////////
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////////////// CROSS-BAR INTERCONECTION//////////////////////////
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