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[/] [theia_gpu/] [branches/] [icarus_version/] [rtl/] [aDefinitions.v] - Diff between revs 174 and 176

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Rev 174	Rev 176
Line 28...	Line 28...
`for simulation perfomance reasons mainly.`	`for simulation perfomance reasons mainly.`
`*******************************************************************************/`	`*******************************************************************************/`
//`define VERILATOR 1	//`define VERILATOR 1
`define MAX_CORES 4 //The number of cores, make sure you update MAX_CORE_BITS!	`define MAX_CORES 4 //The number of cores, make sure you update MAX_CORE_BITS!
`define MAX_CORE_BITS 2 // 2 ^ MAX_CORE_BITS = MAX_CORES	`define MAX_CORE_BITS 2 // 2 ^ MAX_CORE_BITS = MAX_CORES
`define MAX_TMEM_BANKS 4 //The number of memory banks for TMEM	`define MAX_TMEM_BANKS 8 //The number of memory banks for TMEM
	`define MAX_TMEM_BITS 3 //2 ^ MAX_TMEM_BANKS = MAX_TMEM_BITS
`define SELECT_ALL_CORES `MAX_CORES'b1111 //XXX: Change for more cores	`define SELECT_ALL_CORES `MAX_CORES'b1111 //XXX: Change for more cores
`//---------------------------------------------------------------------------------`	`//---------------------------------------------------------------------------------`
//Verilog provides a `default_nettype none compiler directive. When	//Verilog provides a `default_nettype none compiler directive. When
`//this directive is set, implicit data types are disabled, which will make any`	`//this directive is set, implicit data types are disabled, which will make any`
`//undeclared signal name a syntax error.This is very usefull to avoid annoying`	`//undeclared signal name a syntax error.This is very usefull to avoid annoying`

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