| Line 54... |
Line 54... |
input wire [`MAX_TMEM_BANKS-1:0] iTMEM_Sel,
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input wire [`MAX_TMEM_BANKS-1:0] iTMEM_Sel,
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input wire [`MAX_CORE_BITS-1:0] iOMEMBankSelect,
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input wire [`MAX_CORE_BITS-1:0] iOMEMBankSelect,
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input wire [`WB_WIDTH-1:0] iOMEMReadAddress,
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input wire [`WB_WIDTH-1:0] iOMEMReadAddress,
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output wire [`WB_WIDTH-1:0] oOMEMData, //Output data bus (Wishbone)
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output wire [`WB_WIDTH-1:0] oOMEMData, //Output data bus (Wishbone)
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`ifndef NO_DISPLAY_STATS
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`ifndef NO_DISPLAY_STATS
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input wire [`WIDTH-1:0] iDebugWidth,
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input wire [`WIDTH-1:0] iWidth,iHeight,
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`endif
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`endif
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output wire oDone
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output wire oDone
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);
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);
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wire wHost_2__RenderDone;
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assign oDone = wHost_2__RenderDone;
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assign oMemSelect = wMemSelect;
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assign oMemSelect = wMemSelect;
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wire [`WB_WIDTH-1:0] wHost_2__DAT_O;
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wire [`WB_WIDTH-1:0] wHost_2__DAT_O;
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reg wHost_2__ACK;
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reg wHost_2__ACK;
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| Line 81... |
Line 83... |
wire wHost_2__STDONE;
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wire wHost_2__STDONE;
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wire wGPUCommitedResults;
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wire wGPUCommitedResults;
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wire wHostDataAvailable;
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wire wHostDataAvailable;
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wire wHost_2__CYC_O,wHost_2__GACK_O,TGC_O,wHost_2__STB_O;
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wire wHost_2__CYC_O,wHost_2__GACK_O,TGC_O,wHost_2__STB_O;
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assign oDone = wGPU_2_HOST_Done;
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//assign oDone = wGPU_2_HOST_Done;
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THEIA GPU
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THEIA GPU
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(
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(
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.CLK_I( Clock ),
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.CLK_I( Clock ),
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.RST_I( Reset ),
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.RST_I( Reset ),
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| Line 144... |
Line 146... |
.iMemorySize( iMemorySize ),
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.iMemorySize( iMemorySize ),
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.iPrimitiveCount( iPrimitiveCount ),
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.iPrimitiveCount( iPrimitiveCount ),
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.iGPUCommitedResults( wGPUCommitedResults ),
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.iGPUCommitedResults( wGPUCommitedResults ),
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.STDONE_O( wHost_2__STDONE ),
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.STDONE_O( wHost_2__STDONE ),
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.iGPUDone( wGPU_2_HOST_Done ),
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.iGPUDone( wGPU_2_HOST_Done ),
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.oRenderDone( wHost_2__RenderDone ),
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`ifndef NO_DISPLAY_STATS
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.iDebugWidth(iDebugWidth),
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.iWidth(iWidth),
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`endif
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.iHeight(iHeight),
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//To Memory
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//To Memory
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.oReadAddress( oHostReadAddress ),
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.oReadAddress( oHostReadAddress ),
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.iReadData( wHostReadData ),
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.iReadData( wHostReadData ),
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