URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [icarus_version/] [simulation/] [Makefile] - Diff between revs 172 and 177

Rev 172	Rev 177
Line 9...	Line 9...
`GPUCONFIGURATIONSCRIPT=../scripts/configure_gpu.pl`	`GPUCONFIGURATIONSCRIPT=../scripts/configure_gpu.pl`
`INPUTCONFIGURATIONSCRIPT=../scripts/configure_params.pl`	`INPUTCONFIGURATIONSCRIPT=../scripts/configure_params.pl`
`#iverilog CONFIG`	`#iverilog CONFIG`
`VERILOG_CMD = iverilog`	`VERILOG_CMD = iverilog`
`GPUCORES = 4`	`GPUCORES = 4`
	`GPUMEMBANKS = $(GPUCORES)`
`#VERILOG_FLAGS =`	`#VERILOG_FLAGS =`

`# VVP (iverilog runtime engine)`	`# VVP (iverilog runtime engine)`
`VVP_CMD = vvp`	`VVP_CMD = vvp`
`#VVP_FLAGS =`	`#VVP_FLAGS =`
Line 50...	Line 51...
`echo "Setting up project ${PROJECT}"`	`echo "Setting up project ${PROJECT}"`
`mkdir rtl testbench simulation`	`mkdir rtl testbench simulation`


`compile : testbench_check`	`compile : testbench_check`
`perl $(GPUCONFIGURATIONSCRIPT) $(GPUCORES)`	`perl $(GPUCONFIGURATIONSCRIPT) $(GPUCORES) $(GPUMEMBANKS)`

`cp $(SOURCEPATH)/aDefinitions.v .`	`cp $(SOURCEPATH)/aDefinitions.v .`
`ifeq ($(strip $(DEBUG_CORE_ID)),)`	`ifeq ($(strip $(DEBUG_CORE_ID)),)`
`$(VERILOG_CMD) -o $(SIMDIR)/$(TESTBENCH) $(TESTBENCHPATH) $(SOURCEPATH)/*`	`$(VERILOG_CMD) -o $(SIMDIR)/$(TESTBENCH) $(TESTBENCHPATH) $(SOURCEPATH)/*`
`else`	`else`
Line 73...	Line 74...

`view : testbench_check`	`view : testbench_check`
`$(WAVEFORM_VIEWER) $(SIMDIR)/$(TESTBENCH).$(DUMPTYPE)`	`$(WAVEFORM_VIEWER) $(SIMDIR)/$(TESTBENCH).$(DUMPTYPE)`

`clean :`	`clean :`
`rm -f *.mem`	`rm *.{mem,ppm,log}`
`rm -f *.ppm`
`rm -f *.log`
`rm *.{mem,ppm,log}`