OpenCores
URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [branches/] [icarus_version/] [testbench/] [TestBench_verilog.v] - Diff between revs 193 and 195

Show entire file | Details | Blame | View Log

Rev 193 Rev 195
Line 38... Line 38...
`include "aDefinitions.v"
`include "aDefinitions.v"
`define RESOLUTION_WIDTH        (rSceneParameters[13] >> `SCALE)
`define RESOLUTION_WIDTH        (rSceneParameters[13] >> `SCALE)
`define RESOLUTION_HEIGHT        (rSceneParameters[14] >> `SCALE)
`define RESOLUTION_HEIGHT        (rSceneParameters[14] >> `SCALE)
`define DELTA_ROW          (32'h1 << `SCALE)
`define DELTA_ROW          (32'h1 << `SCALE)
`define DELTA_COL          (32'h1 << `SCALE)
`define DELTA_COL          (32'h1 << `SCALE)
`define TEXTURE_BUFFER_SIZE       (256*256*3)
 
`define MAX_WIDTH          200
`define MAX_WIDTH          200
`define MAX_SCREENBUFFER        (`MAX_WIDTH*`MAX_WIDTH*3)
`define MAX_SCREENBUFFER        (`MAX_WIDTH*`MAX_WIDTH*3)
module TestBench_Theia;
module TestBench_Theia;
 
 
 
 
Line 65... Line 65...
 reg [`WB_WIDTH-1:0]    TMADR_O,TMDAT_O;
 reg [`WB_WIDTH-1:0]    TMADR_O,TMDAT_O;
 reg [`MAX_TMEM_BANKS-1:0]  TMSEL_O;
 reg [`MAX_TMEM_BANKS-1:0]  TMSEL_O;
 reg         TMWE_O;
 reg         TMWE_O;
 reg [31:0]       rControlRegister[2:0];
 reg [31:0]       rControlRegister[2:0];
 integer          file, log;
 integer          file, log;
 reg [31:0]       rSceneParameters[512:0];
 reg [31:0]       rSceneParameters[`PARAMS_ARRAY_SIZE-1:0];
 reg [31:0]       rVertexBuffer[7000:0];
 reg [31:0]       rVertexBuffer[`VERTEX_ARRAY_SIZE-1:0];
 reg [31:0]       rInstructionBuffer[512:0];
 reg [31:0]       rInstructionBuffer[512:0];
 reg [31:0]       rTextures[`TEXTURE_BUFFER_SIZE:0];  //Lets asume we use 256*256 textures
 reg [31:0]       rTextures[`TEXTURE_BUFFER_SIZE-1:0];  //Lets asume we use 256*256 textures
 reg [7:0]        rScreen[`MAX_SCREENBUFFER-1:0];
 reg [7:0]        rScreen[`MAX_SCREENBUFFER-1:0];
 
 
 wire         wDone;
 wire         wDone;
 wire [`MAX_CORES-1:0]   RENDREN_O;
 wire [`MAX_CORES-1:0]   RENDREN_O;
 reg [`MAX_CORE_BITS-1:0]   wOMEMBankSelect;
 reg [`MAX_CORE_BITS-1:0]   wOMEMBankSelect;
Line 151... Line 151...
begin
begin
 
 
 
 
if (wDone == 1'b1)
if (wDone == 1'b1)
begin
begin
 
 $fwrite(log, "Simulation end time : %dns\n",$time);
 
 
 $display("Partition Size = %d",`PARTITION_SIZE);
 $display("Partition Size = %d",`PARTITION_SIZE);
 for (kk = 0; kk < `MAX_CORES; kk = kk+1)
 for (kk = 0; kk < `MAX_CORES; kk = kk+1)
   begin
   begin
   wOMEMBankSelect = kk;
   wOMEMBankSelect = kk;
Line 178... Line 179...
   end
   end
 
 
 
 
 
 
   $fclose(out2);
   $fclose(out2);
   $fwrite(log, "Simulation end time : %dns\n",$time);
 
   $fclose(log);
   $fclose(log);
 
 
 
 
   $stop();
   $stop();
 
 
Line 269... Line 270...
   begin
   begin
    $write("|");
    $write("|");
    $fflush;
    $fflush;
   end
   end
  end
  end
 
 
  $display("\nDone Intilializing TMEM @ %dns",$time);
  $display("\nDone Intilializing TMEM @ %dns",$time);
  TMWE_O = 0;
  TMWE_O = 0;
  rHostEnable = 1;
  rHostEnable = 1;
 
 
  log  = $fopen("Simulation.log");
  log  = $fopen("Simulation.log");
  $fwrite(log, "Simulation start time : %dns\n",$time);
  $fwrite(log, "Simulation start time : %dns\n",$time);
  $fwrite(log, "Width : %d\n",`RESOLUTION_WIDTH);
 
  $fwrite(log, "Height : %d\n",`RESOLUTION_HEIGHT);
 
 
 
  //Start dumping VCD
  //Start dumping VCD
  $display("-I- Starting VCD Dump\n");
  $display("-I- Starting VCD Dump\n");
  $dumpfile("TestBench_Theia.vcd");
  $dumpfile("TestBench_Theia.vcd");
  $dumpvars(0,TestBench_Theia);
  $dumpvars(0,TestBench_Theia);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.