| Line 20... |
Line 20... |
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***********************************************************************************/
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***********************************************************************************/
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/*
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/*
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The memory unit has all the memory related modules for THEIA.
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The memory unit has all the memory related modules for THEIA.
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There a 3 memories in the core:
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There a 3 memories in the core:
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DMEM: The data memory, it is a R/W RAM, stores the data locations.
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DMEM: The data memory, it is a R/W dual channel RAM, stores the data locations.
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IMEM: The instruction memory, R/W RAM, stores user shaders.
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IMEM: The instruction memory, R/W dual channel RAM, stores user shaders.
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IROM: RO instruction memory, stores default shaders and other internal code.
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IROM: RO instruction memory, stores default shaders and other internal code.
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I use two ROMs with the same data, so that simulates dual channel.
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This unit also has a Control register.
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This unit also has a Control register.
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*/
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*/
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`define USER_CODE_ENABLED 2
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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module MemoryUnit
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module MemoryUnit
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(
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(
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input wire Clock,
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input wire Clock,
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input wire Reset,
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input wire Reset,
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input wire iDataWriteEnable,
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input wire iDataWriteEnable,
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input wire iInstructionWriteEnable,
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input wire iInstructionWriteEnable,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionReadAddress,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionReadAddress1,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionReadAddress2,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionWriteAddress,
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input wire [`ROM_ADDRESS_WIDTH-1:0] iInstructionWriteAddress,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstruction,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstruction1,
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output wire [`INSTRUCTION_WIDTH-1:0] oInstruction2,
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input wire [`INSTRUCTION_WIDTH-1:0] iInstruction,
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input wire [`INSTRUCTION_WIDTH-1:0] iInstruction,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress1,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress1,
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input wire[`DATA_ROW_WIDTH-1:0] oData1,
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input wire[`DATA_ROW_WIDTH-1:0] oData1,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress2,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDataReadAddress2,
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input wire[`DATA_ROW_WIDTH-1:0] oData2,
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input wire[`DATA_ROW_WIDTH-1:0] oData2,
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| Line 48... |
Line 52... |
output wire[15:0] oControlRegister
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output wire[15:0] oControlRegister
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);
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);
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wire [`ROM_ADDRESS_WIDTH-1:0] wROMInstructionAddress,wRAMInstructionAddress;
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wire [`ROM_ADDRESS_WIDTH-1:0] wROMInstructionAddress,wRAMInstructionAddress;
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wire [`INSTRUCTION_WIDTH-1:0] wIMEM2_IMUX__DataOut,wIROM2_IMUX__DataOut;
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wire [`INSTRUCTION_WIDTH-1:0] wIMEM2_IMUX__DataOut1,wIMEM2_IMUX__DataOut2,
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wIROM2_IMUX__DataOut1,wIROM2_IMUX__DataOut2;
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assign oInstruction = (iInstructionReadAddress[`ROM_ADDRESS_WIDTH-1] == 1) ?
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wire wInstructionSelector;
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wIMEM2_IMUX__DataOut : wIROM2_IMUX__DataOut;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1
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(
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.Clock(Clock),
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.Reset(Reset),
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.Enable( 1'b1 ),
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.D( iInstructionReadAddress1[`ROM_ADDRESS_WIDTH-1] ),
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.Q( wInstructionSelector )
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);
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assign oInstruction1 = (wInstructionSelector == 1) ?
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wIMEM2_IMUX__DataOut1 : wIROM2_IMUX__DataOut1;
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assign oInstruction2 = (wInstructionSelector == 1) ?
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wIMEM2_IMUX__DataOut2 : wIROM2_IMUX__DataOut2;
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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/*
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/*
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Data memory.
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Data memory.
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*/
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*/
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RAM_DATA DMEM
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RAM_128_ROW_DUAL_READ_PORT # (`DATA_ROW_WIDTH,`DATA_ADDRESS_WIDTH) DMEM
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.iWriteEnable( iDataWriteEnable ),
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.iWriteEnable( iDataWriteEnable ),
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.iReadAddress0( iDataReadAddress1 ),
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.iReadAddress0( iDataReadAddress1 ),
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.iReadAddress1( iDataReadAddress2 ),
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.iReadAddress1( iDataReadAddress2 ),
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| Line 73... |
Line 91... |
);
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);
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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/*
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/*
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Instruction memory.
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Instruction memory.
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*/
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*/
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RAM_INST IMEM
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RAM_128_ROW_DUAL_READ_PORT # (`INSTRUCTION_WIDTH,`ROM_ADDRESS_WIDTH) IMEM
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.iWriteEnable( iInstructionWriteEnable ),
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.iWriteEnable( iInstructionWriteEnable ),
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.iReadAddress( iInstructionReadAddress ),
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.iReadAddress0( {1'b0,iInstructionReadAddress1[`ROM_ADDRESS_WIDTH-2:0]} ),
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.iReadAddress1( {1'b0,iInstructionReadAddress2[`ROM_ADDRESS_WIDTH-2:0]} ),
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.iWriteAddress( iInstructionWriteAddress ),
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.iWriteAddress( iInstructionWriteAddress ),
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.iDataIn( iInstruction ),
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.iDataIn( iInstruction ),
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.oDataOut( wIMEM2_IMUX__DataOut )
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.oDataOut0( wIMEM2_IMUX__DataOut1 ),
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.oDataOut1( wIMEM2_IMUX__DataOut2 )
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|
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);
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);
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//-------------------------------------------------------------------
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//-------------------------------------------------------------------
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/*
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/*
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Default code stored in ROM.
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Default code stored in ROM.
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*/
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*/
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wire [`INSTRUCTION_WIDTH-1:0] wRomDelay1,wRomDelay2;
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//In real world ROM will take at least 1 clock cycle,
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//since ROMs are not syhtethizable, I won't hurt to put
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//this delay
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|
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_WIDTH ) FFDA
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(
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.Clock(Clock),
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.Reset(Reset),
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.Enable(1'b1),
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.D(wRomDelay1),
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.Q(wIROM2_IMUX__DataOut1 )
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_WIDTH ) FFDB
|
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(
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.Clock(Clock),
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.Reset(Reset),
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.Enable(1'b1),
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.D(wRomDelay2),
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.Q(wIROM2_IMUX__DataOut2 )
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);
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//The reason I put two ROMs is because I need to read 2 different Instruction
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//addresses at the same time (branch-taken and branch-not-taken) and not sure
|
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//hpw to write dual read channel ROM this way...
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|
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ROM IROM
|
ROM IROM
|
(
|
(
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.Address( iInstructionReadAddress ),
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.Address( {1'b0,iInstructionReadAddress1[`ROM_ADDRESS_WIDTH-2:0]} ),
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.I( wIROM2_IMUX__DataOut )
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.I( wRomDelay1 )
|
|
);
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|
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ROM IROM2
|
|
(
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.Address( {1'b0,iInstructionReadAddress2[`ROM_ADDRESS_WIDTH-2:0]} ),
|
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.I( wRomDelay2 )
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);
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);
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//--------------------------------------------------------
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//--------------------------------------------------------
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ControlRegister CR
|
ControlRegister CR
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
