| Line 38... |
Line 38... |
output wire [`WIDTH-1:0] oResultB,
|
output wire [`WIDTH-1:0] oResultB,
|
output wire [`WIDTH-1:0] oResultC,
|
output wire [`WIDTH-1:0] oResultC,
|
input wire iInputReady,
|
input wire iInputReady,
|
output reg oBranchTaken,
|
output reg oBranchTaken,
|
output reg oBranchNotTaken,
|
output reg oBranchNotTaken,
|
|
output reg oReturnFromSub,
|
|
input wire [`ROM_ADDRESS_WIDTH-1:0] iCurrentIP,
|
|
|
|
//Connections to the O Memory
|
|
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteAddress,
|
|
output wire [`DATA_ROW_WIDTH-1:0] oOMEMWriteData,
|
|
output wire oOMEM_WriteEnable,
|
|
//Connections to the R Memory
|
|
output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadAddress,
|
|
input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadData,
|
|
input wire iTMEMDataAvailable,
|
|
output wire oTMEMDataRequest,
|
|
|
output reg OutputReady
|
output reg OutputReady
|
|
|
);
|
);
|
|
|
|
|
|
|
|
|
|
|
wire wMultiplcationUnscaled;
|
wire wMultiplcationUnscaled;
|
assign wMultiplcationUnscaled = (iOperation == `IMUL) ? 1'b1 : 1'b0;
|
assign wMultiplcationUnscaled = (iOperation == `IMUL) ? 1'b1 : 1'b0;
|
|
|
//--------------------------------------------------------------
|
//--------------------------------------------------------------
|
|
|
| Line 111... |
Line 128... |
.SwizzleY( wSwizzleOutputY ),
|
.SwizzleY( wSwizzleOutputY ),
|
.SwizzleZ( wSwizzleOutputZ )
|
.SwizzleZ( wSwizzleOutputZ )
|
);
|
);
|
//---------------------------------------------------------------------
|
//---------------------------------------------------------------------
|
wire [`LONG_WIDTH-1:0] wModulus2N_ResultA,wModulus2N_ResultB,wModulus2N_ResultC;
|
wire [`LONG_WIDTH-1:0] wModulus2N_ResultA,wModulus2N_ResultB,wModulus2N_ResultC;
|
//wire wModulusOutputReadyA,wModulusOutputReadyB,wModulusOutputReadyC;
|
|
|
|
/*
|
//---------------------------------------------------------------------(
|
Modulus2N MODA
|
|
(
|
wire IOW_Operation,wOMEM_We;
|
.Clock( Clock ),
|
assign IOW_Operation = (iOperation == `OMWRITE);
|
.Reset( Reset ),
|
|
.oQuotient( wModulus2N_ResultA ),
|
always @ ( * )
|
.iInputReady( iInputReady ),
|
begin
|
.oOutputReady( wModulusOutputReadyA )
|
if (iOperation == `RET)
|
);
|
oReturnFromSub <= OutputReady;
|
|
else
|
|
oReturnFromSub <= 1'b0;
|
|
|
|
end
|
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1_AWE
|
|
(
|
|
.Clock( Clock ),
|
|
.Reset( Reset),
|
|
.Enable( 1'b1 ),
|
|
.D( IOW_Operation ),
|
|
.Q( wOMEM_We )
|
|
);
|
|
|
|
assign oOMEM_WriteEnable = wOMEM_We & IOW_Operation;
|
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD1_A
|
|
(
|
|
.Clock( Clock ),
|
|
.Reset( Reset),
|
|
.Enable( iInputReady ),
|
|
.D( {iChannel_Ax,iChannel_Ay,iChannel_Az} ),
|
|
.Q( oOMEMWriteAddress)
|
|
);
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD2_B
|
|
(
|
|
.Clock( Clock ),
|
|
.Reset( Reset),
|
|
.Enable( iInputReady ),
|
|
.D( {iChannel_Bx,iChannel_By,iChannel_Bz} ),
|
|
.Q( oOMEMWriteData )
|
|
);
|
|
|
Modulus2N MODB
|
|
(
|
|
.Clock( Clock ),
|
|
.Reset( Reset ),
|
|
.oQuotient( wModulus2N_ResultB ),
|
|
.iInputReady( iInputReady ),
|
|
.oOutputReady( wModulusOutputReadyB )
|
|
);
|
|
|
|
Modulus2N MODC
|
|
|
wire wTMReadOutputReady;
|
|
assign wTMReadOutputReady = iTMEMDataAvailable;
|
|
/*
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1_ARE
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Reset( Reset ),
|
.Reset( Reset ),
|
.oQuotient( wModulus2N_ResultC ),
|
.Enable( 1'b1 ),
|
.iInputReady( iInputReady ),
|
.D( iTMEMDataAvailable ),
|
.oOutputReady( wModulusOutputReadyC )
|
.Q( wTMReadOutputReady )
|
);
|
);
|
*/
|
*/
|
//---------------------------------------------------------------------(
|
//assign oTMEMReadAddress = {iChannel_Ax,iChannel_Ay,iChannel_Az};
|
|
|
|
|
|
//We wait 1 clock cycle before be send the data read request, because
|
|
//we need to lathc the values at the output
|
|
|
|
wire wOpTRead;
|
|
assign wOpTRead = ( iOperation == `TMREAD ) ? 1'b1 : 1'b0;
|
|
wire wTMEMRequest;
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFD1_ARE123
|
|
(
|
|
.Clock( Clock ),
|
|
.Reset( Reset),
|
|
.Enable( 1'b1 ),
|
|
.D( wOpTRead ),
|
|
.Q( wTMEMRequest )
|
|
);
|
|
assign oTMEMDataRequest = wTMEMRequest & wOpTRead;
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ROW_WIDTH ) FFD2_B445
|
|
(
|
|
.Clock( Clock ),
|
|
.Reset( Reset),
|
|
.Enable( iInputReady & wOpTRead ),
|
|
.D( {iChannel_Ax,iChannel_Ay,iChannel_Az} ),
|
|
.Q( oTMEMReadAddress )
|
|
);
|
|
|
/*
|
/*
|
This MUX will select the apropiated X,Y or Z depending on
|
This MUX will select the apropiated X,Y or Z depending on
|
wheter it is XYZ iOperation. This gets defined by the bits 3 and 4
|
wheter it is XYZ iOperation. This gets defined by the bits 3 and 4
|
of iOperation, and only applies for oBranchTaken and Store operations.
|
of iOperation, and only applies for oBranchTaken and Store operations.
|
| Line 864... |
Line 929... |
`IMUL: ResultA = wMultiplicationA_Result[31:0];
|
`IMUL: ResultA = wMultiplicationA_Result[31:0];
|
`DOT: ResultA = (wAddSubB_Result[63] == 1'b1) ? { 1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0];
|
`DOT: ResultA = (wAddSubB_Result[63] == 1'b1) ? { 1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0];
|
`MAG: ResultA = wSquareRoot_Result;
|
`MAG: ResultA = wSquareRoot_Result;
|
`ZERO: ResultA = 32'b0;
|
`ZERO: ResultA = 32'b0;
|
`COPY: ResultA = iChannel_Ax;
|
`COPY: ResultA = iChannel_Ax;
|
|
`TMREAD: ResultA = iTMEMReadData[95:64];
|
|
`LEA: ResultA = {16'b0,iCurrentIP};
|
|
|
`SWIZZLE3D: ResultA = wSwizzleOutputX;
|
`SWIZZLE3D: ResultA = wSwizzleOutputX;
|
|
|
//Set Operations
|
//Set Operations
|
`UNSCALE: ResultA = iChannel_Ax >> `SCALE;
|
`UNSCALE: ResultA = iChannel_Ax >> `SCALE;
|
`SETX: ResultA = iChannel_Ax;
|
`SETX,`RET: ResultA = iChannel_Ax;
|
`SETY: ResultA = iChannel_Bx;
|
`SETY: ResultA = iChannel_Bx;
|
`SETZ: ResultA = iChannel_Bx;
|
`SETZ: ResultA = iChannel_Bx;
|
`INC,`INCX,`INCY,`INCZ: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};
|
`INC,`INCX,`INCY,`INCZ: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};
|
`DEC: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};
|
`DEC: ResultA = (wAddSubA_Result[63] == 1'b1) ? { 1'b1,wAddSubA_Result[30:0]} : {1'b0,wAddSubA_Result[30:0]};
|
`MOD: ResultA = wModulus2N_ResultA;
|
`MOD: ResultA = wModulus2N_ResultA;
|
| Line 906... |
Line 973... |
`IMUL: ResultB = wMultiplicationB_Result[31:0];
|
`IMUL: ResultB = wMultiplicationB_Result[31:0];
|
`DOT: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0];
|
`DOT: ResultB = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0];
|
`MAG: ResultB = wSquareRoot_Result;
|
`MAG: ResultB = wSquareRoot_Result;
|
`ZERO: ResultB = 32'b0;
|
`ZERO: ResultB = 32'b0;
|
`COPY: ResultB = iChannel_Ay;
|
`COPY: ResultB = iChannel_Ay;
|
|
`TMREAD: ResultB = iTMEMReadData[63:32];
|
|
`LEA: ResultB = {16'b0,iCurrentIP};
|
|
|
//Set Operations
|
//Set Operations
|
`UNSCALE: ResultB = iChannel_Ay >> `SCALE;
|
`UNSCALE: ResultB = iChannel_Ay >> `SCALE;
|
`SETX: ResultB = iChannel_By; // {Source1[95:64],Source0[63:32],Source0[31:0]};
|
`SETX,`RET: ResultB = iChannel_By; // {Source1[95:64],Source0[63:32],Source0[31:0]};
|
`SETY: ResultB = iChannel_Ax; // {Source0[95:64],Source1[95:64],Source0[31:0]};
|
`SETY: ResultB = iChannel_Ax; // {Source0[95:64],Source1[95:64],Source0[31:0]};
|
`SETZ: ResultB = iChannel_By; // {Source0[95:64],Source0[63:32],Source1[95:64]};
|
`SETZ: ResultB = iChannel_By; // {Source0[95:64],Source0[63:32],Source1[95:64]};
|
|
|
`SWIZZLE3D: ResultB = wSwizzleOutputY;
|
`SWIZZLE3D: ResultB = wSwizzleOutputY;
|
|
|
| Line 949... |
Line 1018... |
`IMUL: ResultC = wMultiplicationC_Result[31:0];
|
`IMUL: ResultC = wMultiplicationC_Result[31:0];
|
`DOT: ResultC = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0];
|
`DOT: ResultC = (wAddSubB_Result[63] == 1'b1) ? {1'b1,wAddSubB_Result[30:0]} : {1'b0,wAddSubB_Result[30:0]};//wAddSubB_Result[31:0];
|
`MAG: ResultC = wSquareRoot_Result;
|
`MAG: ResultC = wSquareRoot_Result;
|
`ZERO: ResultC = 32'b0;
|
`ZERO: ResultC = 32'b0;
|
`COPY: ResultC = iChannel_Az;
|
`COPY: ResultC = iChannel_Az;
|
|
`TMREAD: ResultC = iTMEMReadData[31:0];
|
|
`LEA: ResultC = {16'b0,iCurrentIP};
|
|
|
`SWIZZLE3D: ResultC = wSwizzleOutputZ;
|
`SWIZZLE3D: ResultC = wSwizzleOutputZ;
|
|
|
//Set Operations
|
//Set Operations
|
`UNSCALE: ResultC = iChannel_Az >> `SCALE;
|
`UNSCALE: ResultC = iChannel_Az >> `SCALE;
|
`SETX: ResultC = iChannel_Bz; // {Source1[95:64],Source0[63:32],Source0[31:0]};
|
`SETX,`RET: ResultC = iChannel_Bz; // {Source1[95:64],Source0[63:32],Source0[31:0]};
|
`SETY: ResultC = iChannel_Bz; // {Source0[95:64],Source1[95:64],Source0[31:0]};
|
`SETY: ResultC = iChannel_Bz; // {Source0[95:64],Source1[95:64],Source0[31:0]};
|
`SETZ: ResultC = iChannel_Ax; // {Source0[95:64],Source0[63:32],Source1[95:64]};
|
`SETZ: ResultC = iChannel_Ax; // {Source0[95:64],Source0[63:32],Source1[95:64]};
|
|
|
`INC,`INCX,`INCY,`INCZ: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF;
|
`INC,`INCX,`INCY,`INCZ: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF;
|
`DEC: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF;
|
`DEC: ResultC = (wAddSubC_Result[63] == 1'b1) ? {1'b1,wAddSubC_Result[30:0]} : {1'b0,wAddSubC_Result[30:0]}; //wAddSubC_Result[31:0];// & 32'h7FFFFFFF;
|
| Line 981... |
Line 1052... |
|
|
|
|
always @ ( * )
|
always @ ( * )
|
begin
|
begin
|
case (iOperation)
|
case (iOperation)
|
`JMP: oBranchTaken = 1;
|
`JMP,`CALL,`RET: oBranchTaken = OutputReady;
|
`JGX: oBranchTaken = wArithmeticComparison_Result;
|
`JGX: oBranchTaken = wArithmeticComparison_Result;
|
`JGY: oBranchTaken = wArithmeticComparison_Result;
|
`JGY: oBranchTaken = wArithmeticComparison_Result;
|
`JGZ: oBranchTaken = wArithmeticComparison_Result;
|
`JGZ: oBranchTaken = wArithmeticComparison_Result;
|
|
|
`JLX: oBranchTaken = wArithmeticComparison_Result;
|
`JLX: oBranchTaken = wArithmeticComparison_Result;
|
| Line 1015... |
Line 1086... |
|
|
always @ ( * )
|
always @ ( * )
|
begin
|
begin
|
case (iOperation)
|
case (iOperation)
|
|
|
`JMP,`JGX,`JGY,`JGZ,`JLX,`JLY,`JLZ,`JEQX,`JEQY,`JEQZ,
|
`JMP,`CALL,`RET,`JGX,`JGY,`JGZ,`JLX,`JLY,`JLZ,`JEQX,`JEQY,`JEQZ,
|
`JNEX,`JNEY,`JNEZ,`JGEX,`JGEY,`JGEZ: oBranchNotTaken = !oBranchTaken && OutputReady;
|
`JNEX,`JNEY,`JNEZ,`JGEX,`JGEY,`JGEZ: oBranchNotTaken = !oBranchTaken && OutputReady;
|
`JLEX: oBranchNotTaken = !oBranchTaken && OutputReady;
|
`JLEX: oBranchNotTaken = !oBranchTaken && OutputReady;
|
`JLEY: oBranchNotTaken = !oBranchTaken && OutputReady;
|
`JLEY: oBranchNotTaken = !oBranchTaken && OutputReady;
|
`JLEZ: oBranchNotTaken = !oBranchTaken && OutputReady;
|
`JLEZ: oBranchNotTaken = !oBranchTaken && OutputReady;
|
default:
|
default:
|
| Line 1083... |
Line 1154... |
.Q( wSquareRootOutputReady )
|
.Q( wSquareRootOutputReady )
|
);
|
);
|
|
|
|
|
//------------------------------------------------------------------------
|
//------------------------------------------------------------------------
|
wire wOutputDelay1Cycle;
|
wire wOutputDelay1Cycle,wOutputDelay2Cycle,wOutputDelay3Cycle;
|
|
|
|
|
FFD_POSEDGE_ASYNC_RESET # (1) FFOutputReadyDelay2
|
FFD_POSEDGE_ASYNC_RESET # (1) FFOutputReadyDelay2
|
(
|
(
|
.Clock( Clock ),
|
.Clock( Clock ),
|
.Clear( Reset ),
|
.Clear( Reset ),
|
.D( iInputReady ),
|
.D( iInputReady ),
|
.Q( wOutputDelay1Cycle )
|
.Q( wOutputDelay1Cycle )
|
);
|
);
|
|
|
|
FFD_POSEDGE_ASYNC_RESET # (1) FFOutputReadyDelay22
|
|
(
|
|
.Clock( Clock ),
|
|
.Clear( Reset ),
|
|
.D( wOutputDelay1Cycle ),
|
|
.Q( wOutputDelay2Cycle )
|
|
);
|
|
|
|
|
|
FFD_POSEDGE_ASYNC_RESET # (1) FFOutputReadyDelay222
|
|
(
|
|
.Clock( Clock && wOperation == `OMWRITE),
|
|
.Clear( Reset ),
|
|
.D( wOutputDelay2Cycle ),
|
|
.Q( wOutputDelay3Cycle )
|
|
);
|
|
|
wire [`INSTRUCTION_OP_LENGTH-1:0] wOperation;
|
wire [`INSTRUCTION_OP_LENGTH-1:0] wOperation;
|
|
|
|
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_OP_LENGTH ) SourceZ2
|
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_OP_LENGTH ) SourceZ2
|
(
|
(
|
| Line 1117... |
Line 1205... |
`RETURN: OutputReady = wOutputDelay1Cycle;
|
`RETURN: OutputReady = wOutputDelay1Cycle;
|
|
|
`NOP: OutputReady = wOutputDelay1Cycle;
|
`NOP: OutputReady = wOutputDelay1Cycle;
|
`FRAC: OutputReady = wOutputDelay1Cycle;
|
`FRAC: OutputReady = wOutputDelay1Cycle;
|
`NEG: OutputReady = wOutputDelay1Cycle;
|
`NEG: OutputReady = wOutputDelay1Cycle;
|
|
`OMWRITE: OutputReady = wOutputDelay3Cycle;
|
|
`TMREAD: OutputReady = wTMReadOutputReady; //One cycle after TMEM data availale asserted
|
|
|
`ifdef DEBUG
|
`ifdef DEBUG
|
//Debug Print behaves as a NOP in terms of ALU...
|
//Debug Print behaves as a NOP in terms of ALU...
|
`DEBUG_PRINT: OutputReady = wOutputDelay1Cycle;
|
`DEBUG_PRINT: OutputReady = wOutputDelay1Cycle;
|
`endif
|
`endif
|
| Line 1151... |
Line 1241... |
|
|
`COPY: OutputReady = wOutputDelay1Cycle;
|
`COPY: OutputReady = wOutputDelay1Cycle;
|
|
|
`SWIZZLE3D: OutputReady = wOutputDelay1Cycle;
|
`SWIZZLE3D: OutputReady = wOutputDelay1Cycle;
|
|
|
`SETX,`SETY,`SETZ,`JMP: OutputReady = wOutputDelay1Cycle;
|
`SETX,`SETY,`SETZ,`JMP,`LEA,`CALL,`RET: OutputReady = wOutputDelay1Cycle;
|
|
|
|
|
|
|
`JGX,`JGY,`JGZ: OutputReady = ArithmeticComparison_OutputReady;
|
`JGX,`JGY,`JGZ: OutputReady = ArithmeticComparison_OutputReady;
|
`JLX,`JLY,`JLZ: OutputReady = ArithmeticComparison_OutputReady;
|
`JLX,`JLY,`JLZ: OutputReady = ArithmeticComparison_OutputReady;
|
`JEQX,`JEQY,`JEQZ: OutputReady = ArithmeticComparison_OutputReady;
|
`JEQX,`JEQY,`JEQZ: OutputReady = ArithmeticComparison_OutputReady;
|
