OpenCores
URL https://opencores.org/ocsvn/theia_gpu/theia_gpu/trunk

Subversion Repositories theia_gpu

[/] [theia_gpu/] [tags/] [latest_stable/] [rtl/] [GPU/] [CORES/] [EXE/] [Module_VectorALU.v] - Diff between revs 60 and 72

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 60 Rev 72
Line 1094... Line 1094...
        .Clear( Reset ),
        .Clear( Reset ),
        .D( iInputReady ),
        .D( iInputReady ),
        .Q( wOutputDelay1Cycle )
        .Q( wOutputDelay1Cycle )
);
);
 
 
 
wire [`INSTRUCTION_OP_LENGTH-1:0] wOperation;
 
 
 
 
 
FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_OP_LENGTH ) SourceZ2
 
(
 
        .Clock( Clock ),
 
        .Reset( Reset ),
 
        .Enable( iInputReady ),
 
        .D( iOperation ),
 
        .Q(wOperation)
 
);
 
 
 
 
//Mux for output ready signal
//Mux for output ready signal
always @ ( * )
always @ ( * )
begin
begin
        case ( iOperation )
        case ( wOperation )
        `UNSCALE:                       OutputReady  = wOutputDelay1Cycle;
        `UNSCALE:                       OutputReady  = wOutputDelay1Cycle;
        `RETURN: OutputReady = wOutputDelay1Cycle;
        `RETURN: OutputReady = wOutputDelay1Cycle;
 
 
        `NOP: OutputReady = wOutputDelay1Cycle;
        `NOP: OutputReady = wOutputDelay1Cycle;
        `FRAC: OutputReady = wOutputDelay1Cycle;
        `FRAC: OutputReady = wOutputDelay1Cycle;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.