| Line 49... |
Line 49... |
output wire oInstructionWriteEnable,
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output wire oInstructionWriteEnable,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oInstructionWriteAddress,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oInstructionWriteAddress,
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inout wire [`WIDTH-1:0] oData,
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inout wire [`WIDTH-1:0] oData,
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output wire oBusy,
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output wire oBusy,
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output wire oDone,
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output wire oDone,
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input wire [`DATA_ROW_WIDTH-1:0] iOMEM_WriteAddress,
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input wire [`DATA_ROW_WIDTH-1:0] iOMEM_WriteData,
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input wire iOMEM_WriteEnable,
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output wire [`WB_WIDTH-1:0] OMEM_DAT_O,
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output wire [`WB_WIDTH-1:0] OMEM_ADR_O,
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output wire OMEM_WE_O,
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//Theia specific interfaces
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//Theia specific interfaces
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input wire MST_I,
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input wire MST_I,
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//Wish Bone Interfaces
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//Wish Bone Interfaces
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output wire [31:0] DAT_O,
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output wire [31:0] DAT_O,
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input wire [31:0] DAT_I,
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input wire [31:0] DAT_I,
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| Line 66... |
Line 75... |
input wire STB_I,
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input wire STB_I,
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output wire CYC_O,
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output wire CYC_O,
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input wire CYC_I,
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input wire CYC_I,
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input wire [1:0] TGA_I,
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input wire [1:0] TGA_I,
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output wire [1:0] TGC_O,
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output wire [1:0] TGC_O,
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input wire GNT_I
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input wire GNT_I,
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output wire [`DATA_ROW_WIDTH-1:0] oTMEMReadData,
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input wire iTMEMDataRequest,
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input wire [`DATA_ROW_WIDTH-1:0] iTMEMReadAddress,
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output wire oTMEMDataAvailable,
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input wire TMEM_ACK_I,
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input wire [`WB_WIDTH-1:0] TMEM_DAT_I ,
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output wire [`WB_WIDTH-1:0] TMEM_ADR_O ,
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output wire TMEM_WE_O,
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output wire TMEM_STB_O,
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output wire TMEM_CYC_O,
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input wire TMEM_GNT_I
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);
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);
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wire [`WIDTH-1:0] wMEMToWBM2__ReadDataElement;
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wire [`WIDTH-1:0] wMEMToWBM2__ReadDataElement;
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wire [`WIDTH-1:0] wMEMToWBM2__ReadDataElement2;
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wire [`WIDTH-1:0] wMEMToWBM2__ReadDataElement2;
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| Line 95... |
Line 118... |
wire wWBSToMEM2__oDataWriteEnable;
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wire wWBSToMEM2__oDataWriteEnable;
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wire[`DATA_ADDRESS_WIDTH-1:0] wWBSToMEM2__oDataWriteAddress;
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wire[`DATA_ADDRESS_WIDTH-1:0] wWBSToMEM2__oDataWriteAddress;
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wire[`DATA_ADDRESS_WIDTH-1:0] wWBMToMEM2__oDataWriteAddress;
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wire[`DATA_ADDRESS_WIDTH-1:0] wWBMToMEM2__oDataWriteAddress;
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//***********new*****************/
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Module_OMemInterface OMI
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(
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.Clock( Clock ),
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.Reset( Reset ),
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.iWriteEnable( iOMEM_WriteEnable ),
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.iData( iOMEM_WriteData ),
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.iAddress( iOMEM_WriteAddress ),
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.ADR_O( OMEM_ADR_O ),
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.DAT_O( OMEM_DAT_O ),
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.WE_O( OMEM_WE_O )
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);
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Module_TMemInterface TMI
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(
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.Clock( Clock ),
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.Reset( Reset ),
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.iEnable( iTMEMDataRequest ),
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.iAddress( iTMEMReadAddress ),
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.oData( oTMEMReadData ),
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.oDone( oTMEMDataAvailable ),
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.ACK_I( TMEM_ACK_I ),
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.GNT_I( TMEM_GNT_I ),
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.DAT_I( TMEM_DAT_I ),
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.ADR_O( TMEM_ADR_O ),
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.WE_O( TMEM_WE_O ),
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.STB_O( TMEM_STB_O ),
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.CYC_O( TMEM_CYC_O )
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);
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//***********new*****************/
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assign oBusy = CYC_O;
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assign oBusy = CYC_O;
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wire wReadOperation;
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wire wReadOperation;
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assign wReadOperation = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? 0 : 1;
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assign wReadOperation = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? 0 : 1;
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| Line 127... |
Line 188... |
assign w2MEMToWBM_BusOperationComplete = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? ACK_I : wWBMToMEM2__Done;
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assign w2MEMToWBM_BusOperationComplete = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? ACK_I : wWBMToMEM2__Done;
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wire [`DATA_ADDRESS_WIDTH-1:0] w2MEMToWBM_DataPointer;
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wire [`DATA_ADDRESS_WIDTH-1:0] w2MEMToWBM_DataPointer;
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assign w2MEMToWBM_DataPointer = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? iDat_O_Pointer : iAdr_O_Pointer;
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assign w2MEMToWBM_DataPointer = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? iDat_O_Pointer : iAdr_O_Pointer;
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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MEM2WBMUnitB MEMToWBM
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MEM2WBMUnitB MEMToWBM
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset ),
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.Reset( Reset ),
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| Line 149... |
Line 212... |
.iDataInitialStorageAddress( iAdr_DataWriteBack ), ////########
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.iDataInitialStorageAddress( iAdr_DataWriteBack ), ////########
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.oDataWriteAddress( wMEMToWBM2_WBMToMEM_RAMWriteAddr ), ////########
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.oDataWriteAddress( wMEMToWBM2_WBMToMEM_RAMWriteAddr ), ////########
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.oDone( wMEMToWBM_2__Done )
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.oDone( wMEMToWBM_2__Done )
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);
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);
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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wire [`DATA_ADDRESS_WIDTH-1:0] wTemp1;
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wire [`DATA_ADDRESS_WIDTH-1:0] wTemp1;
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assign wWBMToMEM2__oDataWriteAddress = (iAdr_O_Type == `ADR_IMM) ? iAdr_DataWriteBack : wTemp1;
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assign wWBMToMEM2__oDataWriteAddress = (iAdr_O_Type == `ADR_IMM) ? iAdr_DataWriteBack : wTemp1;
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WBM2MEMUnit WBMToMEM
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(
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.Clock( Clock ),
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.Reset( Reset ),
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.iEnable( w2WBMToMEM__Enable & (wReadOperation | MST_I) ), //Don't write stuff to MEM unless is Read bus cycle
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.iStore( iStore | ~iAdr_O_Type ),
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.iWriteBack_Set( iWriteBack_Set ),
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.iAdr_DataWriteBack(w2WBMToMEM_MEMWriteAddress ),
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//.iAdr_DataWriteBack( iAdr_DataWriteBack ),
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.iWBMDataAvailable( wWBM_2_WBMToMEM_DataAvailable ),
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.iWBMData( wWBM_2_WBMToMEM_Data ),
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.oDataBus( wWBMToMEM2__oDataBus ),
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.oData( oData ),
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.oEnableWBM( wWBMToMEM_2_WBM_Enable ),
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.oDataWriteAddress( wTemp1 ),///*******************!!!!!!!!!!!!!!
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.oDataWriteEnable( wWBMToMEM2__oDataWriteEnable ),
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.oDone( wWBMToMEM2__Done )
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);
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wire [`WIDTH-1:0] wADR_O_InitialAddress;
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wire [`WIDTH-1:0] wADR_O_InitialAddress;
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assign wADR_O_InitialAddress = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? wMEMToWBM2__ReadDataElement2 : wMEMToWBM_2__Address;
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assign wADR_O_InitialAddress = (iBusCyc_Type == `WB_SIMPLE_WRITE_CYCLE) ? wMEMToWBM2__ReadDataElement2 : wMEMToWBM_2__Address;
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| Line 236... |
Line 284... |
.iAddress( wADR_O_InitialAddress ),
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.iAddress( wADR_O_InitialAddress ),
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.oDataReady( wWBM_2_WBMToMEM_DataAvailable ),
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.oDataReady( wWBM_2_WBMToMEM_DataAvailable ),
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.iData( wMEMToWBM2__ReadDataElement ),
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.iData( wMEMToWBM2__ReadDataElement ),
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.oData( wWBM_2_WBMToMEM_Data )
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.oData( wWBM_2_WBMToMEM_Data )
|
);
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);
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//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
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WishBoneSlaveUnit WBS
|
WishBoneSlaveUnit WBS
|
(
|
(
|
|
|
.CLK_I( Clock ),
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.CLK_I( Clock ),
|
