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[/] [theia_gpu/] [tags/] [latest_stable/] [rtl/] [GPU/] [HOST/] [Module_Host.v] - Diff between revs 124 and 143

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Rev 124 Rev 143
Line 31... Line 31...
 
 
*******************************************************************************/
*******************************************************************************/
 
 
 
 
 
 
`define MAX_VERTEX_IN_FRAME      8'd7 // WAS 8'd6
`define MAX_VERTEX_IN_FRAME      `WIDTH'd7 // WAS 8'd6
`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01
`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01
`define TAG_DATA_ADDRESS_TYPE        2'b10
`define TAG_DATA_ADDRESS_TYPE        2'b10
`define SELECT_INST_MEM              3'b00
`define SELECT_INST_MEM              3'b00
`define SELECT_SCENE_MEM             3'b01
`define SELECT_SCENE_MEM             3'b01
`define SELECT_GEO_MEM               3'b10
`define SELECT_GEO_MEM               3'b10
`define SELECT_ALL_CORES `MAX_CORES'b1111                       //XXX: Change for more cores
 
 
 
`define HOST_IDLE                       0
`define HOST_IDLE                       0
`define HOST_WRITE_INSTRUCTION          1
`define HOST_WRITE_INSTRUCTION          1
`define HOST_WAIT_INSTRUCTION           2
`define HOST_WAIT_INSTRUCTION           2
`define HOST_WRITE_SCENE_PARAMS         3
`define HOST_WRITE_SCENE_PARAMS         3
Line 89... Line 89...
        input  wire                                                     GRDY_I, //This means all the cores are done rading the primitive we send
        input  wire                                                     GRDY_I, //This means all the cores are done rading the primitive we send
   output reg                       GACK_O,     //We set this to ACK that the cored read the primitive
   output reg                       GACK_O,     //We set this to ACK that the cored read the primitive
        output wire                       STDONE_O,
        output wire                       STDONE_O,
        output reg                       oHostDataAvailable,
        output reg                       oHostDataAvailable,
        input wire                       iGPUDone,
        input wire                       iGPUDone,
 
        `ifndef NO_DISPLAY_STATS
 
        input wire [`WIDTH-1:0] iDebugWidth,
 
        `endif
        input wire                       ACK_I
        input wire                       ACK_I
);
);
//---------------------------------------------------------------
//---------------------------------------------------------------
wire wLastPrimitive;
wire wLastPrimitive;
assign wLastPrimitive = (wVertexCount >= iPrimitiveCount) ? 1'b1 : 1'b0;
assign wLastPrimitive = (wVertexCount >= iPrimitiveCount) ? 1'b1 : 1'b0;
Line 102... Line 105...
reg rWBMEnable,rWBMReset,rCoreBroadCast;
reg rWBMEnable,rWBMReset,rCoreBroadCast;
reg [`WB_WIDTH-1:0] rInitiaReadAddr;
reg [`WB_WIDTH-1:0] rInitiaReadAddr;
wire [`MAX_CORES-1:0] wCoreSelect;
wire [`MAX_CORES-1:0] wCoreSelect;
wire wLastValidReadAddress;
wire wLastValidReadAddress;
wire [`WB_WIDTH-1:0] wWriteAddress;
wire [`WB_WIDTH-1:0] wWriteAddress;
wire [7:0] wVertexCount;
wire [`WIDTH-1:0] wVertexCount;
reg [`WB_WIDTH-1:0] rInitialWriteAddress;
reg [`WB_WIDTH-1:0] rInitialWriteAddress;
reg rSetWriteAddr;
reg rSetWriteAddr;
reg rIncCoreSelect,rResetVertexCount;
reg rIncCoreSelect,rResetVertexCount;
//--------------------------------------------------------
//--------------------------------------------------------
 
 
Line 129... Line 132...
        .Initial( rInitialWriteAddress   ),
        .Initial( rInitialWriteAddress   ),
        .Q(       wWriteAddress          )
        .Q(       wWriteAddress          )
        );
        );
 
 
 
 
UPCOUNTER_POSEDGE # (8 ) PRIMCOUNT
UPCOUNTER_POSEDGE # ( 32 ) PRIMCOUNT
        (
        (
        .Clock(  Clock                   ),
        .Clock(  Clock                   ),
        .Reset(   Reset | rResetVertexCount  ),
        .Reset(   Reset | rResetVertexCount  ),
        .Enable(  iEnable & wWBMDone     ),
        .Enable(  iEnable & wWBMDone     ),
        .Initial( 8'b1   ),     //WAS 0
        .Initial( `WIDTH'b1   ),
        .Q(       wVertexCount          )
        .Q(       wVertexCount          )
        );
        );
//--------------------------------------------------------
//--------------------------------------------------------
CIRCULAR_SHIFTLEFT_POSEDGE_EX # (`MAX_CORES ) SHF1
CIRCULAR_SHIFTLEFT_POSEDGE_EX # (`MAX_CORES ) SHF1
(
(
Line 184... Line 187...
          else
          else
                  rHostCurrentState <= `HOST_IDLE;
                  rHostCurrentState <= `HOST_IDLE;
end
end
//--------------------------------------------------------
//--------------------------------------------------------
 
 
 
reg [63:0] i;
 
reg [63:0] RenderedPixels;
wire wLastVertexInFrame;
wire wLastVertexInFrame;
assign wLastVertexInFrame =
assign wLastVertexInFrame =
(wVertexCount % `MAX_VERTEX_IN_FRAME == 1'b0 ) ? 1'b1 : 1'b0;
(wVertexCount % `MAX_VERTEX_IN_FRAME == 1'b0 ) ? 1'b1 : 1'b0;
 
 
// WAS ((wVertexCount % `MAX_VERTEX_IN_FRAME) == 1'b0 && wVertexCount != 0) ? 1'b1 : 1'b0;
// WAS ((wVertexCount % `MAX_VERTEX_IN_FRAME) == 1'b0 && wVertexCount != 0) ? 1'b1 : 1'b0;
Line 202... Line 207...
                //----------------------------------------
                //----------------------------------------
                //Wait for reset sequence to complete,
                //Wait for reset sequence to complete,
                //Or until we are enabled
                //Or until we are enabled
                `HOST_IDLE:
                `HOST_IDLE:
                begin
                begin
 
                RenderedPixels <= 0;
 
 
                        rWBMEnable            <= 0;
                        rWBMEnable            <= 0;
                   rInitiaReadAddr       <= 1;  //Start reading from 1, because 0 is the size
                   rInitiaReadAddr       <= 1;  //Start reading from 1, because 0 is the size
                        rWBMReset             <= 0;
                        rWBMReset             <= 0;
                        oMemSelect            <= 0;
                        oMemSelect            <= 0;
                        TGA_O                 <= 0;
                        TGA_O                 <= 0;
Line 641... Line 648...
                        GACK_O                                   <= 0;
                        GACK_O                                   <= 0;
                        //STDONE_O                                       <= 1;
                        //STDONE_O                                       <= 1;
                        oHostDataAvailable    <= 0;
                        oHostDataAvailable    <= 0;
 
 
 
 
 
 
                        if (iGPUCommitedResults)
                        if (iGPUCommitedResults)
 
                        begin
 
 
 
                        `ifndef NO_DISPLAY_STATS
 
                        for (i = 0; i < `MAX_CORES; i = i + 1)
 
                        begin
 
                                $write(".");
 
                        end
 
                        RenderedPixels = RenderedPixels + `MAX_CORES;
 
                        if ( RenderedPixels % iDebugWidth == 0)
 
                                $write("]%d\n[",RenderedPixels / iDebugWidth);
 
                        `endif
 
 
                                rHostNextState <= `HOST_PREPARE_FOR_GEO_REQUESTS;
                                rHostNextState <= `HOST_PREPARE_FOR_GEO_REQUESTS;
 
                        end
                        else
                        else
                                rHostNextState <= `HOST_LAST_PRIMITIVE_REACHED;
                                rHostNextState <= `HOST_LAST_PRIMITIVE_REACHED;
                end
                end
                //----------------------------------------
                //----------------------------------------
                `HOST_GPU_EXECUTION_DONE:
                `HOST_GPU_EXECUTION_DONE:

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