Line 31... |
Line 31... |
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*******************************************************************************/
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*******************************************************************************/
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`define MAX_VERTEX_IN_FRAME 8'd7 // WAS 8'd6
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`define MAX_VERTEX_IN_FRAME `WIDTH'd7 // WAS 8'd6
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`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01
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`define TAG_INSTRUCTION_ADDRESS_TYPE 2'b01
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`define TAG_DATA_ADDRESS_TYPE 2'b10
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`define TAG_DATA_ADDRESS_TYPE 2'b10
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`define SELECT_INST_MEM 3'b00
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`define SELECT_INST_MEM 3'b00
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`define SELECT_SCENE_MEM 3'b01
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`define SELECT_SCENE_MEM 3'b01
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`define SELECT_GEO_MEM 3'b10
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`define SELECT_GEO_MEM 3'b10
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`define SELECT_ALL_CORES `MAX_CORES'b1111 //XXX: Change for more cores
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`define HOST_IDLE 0
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`define HOST_IDLE 0
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`define HOST_WRITE_INSTRUCTION 1
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`define HOST_WRITE_INSTRUCTION 1
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`define HOST_WAIT_INSTRUCTION 2
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`define HOST_WAIT_INSTRUCTION 2
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`define HOST_WRITE_SCENE_PARAMS 3
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`define HOST_WRITE_SCENE_PARAMS 3
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Line 89... |
Line 89... |
input wire GRDY_I, //This means all the cores are done rading the primitive we send
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input wire GRDY_I, //This means all the cores are done rading the primitive we send
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output reg GACK_O, //We set this to ACK that the cored read the primitive
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output reg GACK_O, //We set this to ACK that the cored read the primitive
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output wire STDONE_O,
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output wire STDONE_O,
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output reg oHostDataAvailable,
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output reg oHostDataAvailable,
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input wire iGPUDone,
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input wire iGPUDone,
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`ifndef NO_DISPLAY_STATS
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input wire [`WIDTH-1:0] iDebugWidth,
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`endif
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input wire ACK_I
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input wire ACK_I
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);
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);
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//---------------------------------------------------------------
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//---------------------------------------------------------------
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wire wLastPrimitive;
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wire wLastPrimitive;
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assign wLastPrimitive = (wVertexCount >= iPrimitiveCount) ? 1'b1 : 1'b0;
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assign wLastPrimitive = (wVertexCount >= iPrimitiveCount) ? 1'b1 : 1'b0;
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Line 102... |
Line 105... |
reg rWBMEnable,rWBMReset,rCoreBroadCast;
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reg rWBMEnable,rWBMReset,rCoreBroadCast;
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reg [`WB_WIDTH-1:0] rInitiaReadAddr;
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reg [`WB_WIDTH-1:0] rInitiaReadAddr;
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wire [`MAX_CORES-1:0] wCoreSelect;
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wire [`MAX_CORES-1:0] wCoreSelect;
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wire wLastValidReadAddress;
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wire wLastValidReadAddress;
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wire [`WB_WIDTH-1:0] wWriteAddress;
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wire [`WB_WIDTH-1:0] wWriteAddress;
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wire [7:0] wVertexCount;
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wire [`WIDTH-1:0] wVertexCount;
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reg [`WB_WIDTH-1:0] rInitialWriteAddress;
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reg [`WB_WIDTH-1:0] rInitialWriteAddress;
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reg rSetWriteAddr;
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reg rSetWriteAddr;
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reg rIncCoreSelect,rResetVertexCount;
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reg rIncCoreSelect,rResetVertexCount;
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//--------------------------------------------------------
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//--------------------------------------------------------
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Line 129... |
Line 132... |
.Initial( rInitialWriteAddress ),
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.Initial( rInitialWriteAddress ),
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.Q( wWriteAddress )
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.Q( wWriteAddress )
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);
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);
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UPCOUNTER_POSEDGE # (8 ) PRIMCOUNT
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UPCOUNTER_POSEDGE # ( 32 ) PRIMCOUNT
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(
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(
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.Clock( Clock ),
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.Clock( Clock ),
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.Reset( Reset | rResetVertexCount ),
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.Reset( Reset | rResetVertexCount ),
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.Enable( iEnable & wWBMDone ),
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.Enable( iEnable & wWBMDone ),
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.Initial( 8'b1 ), //WAS 0
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.Initial( `WIDTH'b1 ),
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.Q( wVertexCount )
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.Q( wVertexCount )
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);
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);
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//--------------------------------------------------------
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//--------------------------------------------------------
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CIRCULAR_SHIFTLEFT_POSEDGE_EX # (`MAX_CORES ) SHF1
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CIRCULAR_SHIFTLEFT_POSEDGE_EX # (`MAX_CORES ) SHF1
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(
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(
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Line 184... |
Line 187... |
else
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else
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rHostCurrentState <= `HOST_IDLE;
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rHostCurrentState <= `HOST_IDLE;
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end
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end
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//--------------------------------------------------------
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//--------------------------------------------------------
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reg [63:0] i;
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reg [63:0] RenderedPixels;
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wire wLastVertexInFrame;
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wire wLastVertexInFrame;
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assign wLastVertexInFrame =
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assign wLastVertexInFrame =
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(wVertexCount % `MAX_VERTEX_IN_FRAME == 1'b0 ) ? 1'b1 : 1'b0;
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(wVertexCount % `MAX_VERTEX_IN_FRAME == 1'b0 ) ? 1'b1 : 1'b0;
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// WAS ((wVertexCount % `MAX_VERTEX_IN_FRAME) == 1'b0 && wVertexCount != 0) ? 1'b1 : 1'b0;
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// WAS ((wVertexCount % `MAX_VERTEX_IN_FRAME) == 1'b0 && wVertexCount != 0) ? 1'b1 : 1'b0;
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Line 202... |
Line 207... |
//----------------------------------------
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//----------------------------------------
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//Wait for reset sequence to complete,
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//Wait for reset sequence to complete,
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//Or until we are enabled
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//Or until we are enabled
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`HOST_IDLE:
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`HOST_IDLE:
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begin
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begin
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RenderedPixels <= 0;
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rWBMEnable <= 0;
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rWBMEnable <= 0;
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rInitiaReadAddr <= 1; //Start reading from 1, because 0 is the size
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rInitiaReadAddr <= 1; //Start reading from 1, because 0 is the size
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rWBMReset <= 0;
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rWBMReset <= 0;
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oMemSelect <= 0;
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oMemSelect <= 0;
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TGA_O <= 0;
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TGA_O <= 0;
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Line 641... |
Line 648... |
GACK_O <= 0;
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GACK_O <= 0;
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//STDONE_O <= 1;
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//STDONE_O <= 1;
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oHostDataAvailable <= 0;
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oHostDataAvailable <= 0;
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if (iGPUCommitedResults)
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if (iGPUCommitedResults)
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begin
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`ifndef NO_DISPLAY_STATS
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for (i = 0; i < `MAX_CORES; i = i + 1)
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begin
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$write(".");
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end
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RenderedPixels = RenderedPixels + `MAX_CORES;
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if ( RenderedPixels % iDebugWidth == 0)
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$write("]%d\n[",RenderedPixels / iDebugWidth);
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`endif
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rHostNextState <= `HOST_PREPARE_FOR_GEO_REQUESTS;
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rHostNextState <= `HOST_PREPARE_FOR_GEO_REQUESTS;
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end
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else
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else
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rHostNextState <= `HOST_LAST_PRIMITIVE_REACHED;
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rHostNextState <= `HOST_LAST_PRIMITIVE_REACHED;
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end
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end
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//----------------------------------------
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//----------------------------------------
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`HOST_GPU_EXECUTION_DONE:
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`HOST_GPU_EXECUTION_DONE:
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