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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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/**********************************************************************************
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Description:
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This is the top level block for THEIA.
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THEIA core has 5 main logical blocks called Units.
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This module implements the interconections between the Units.
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Units:
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> EXE: Mananges execution logic for the SHADERS.
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> GEO: Manages geometry data structures.
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> IO: Input/Output (Wishbone).
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> MEM: Internal memory, separate for Instructions and data.
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> CONTROL: Main control Finite state machine.
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Internal Buses:
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THEIA has separate instruction and data buses.
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THEIA avoids using tri-state buses by having separate input/output
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for each bus.
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There are 2 separate data buses since the Data memory
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has a Dual read channel.
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Please see the MEM unit chapter in the documentation for more details.
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External Buses:
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External buses are managed by the IO Unit.
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External buses follow the wishbone protocol.
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Please see the IO unit chapter in the documentation for more details.
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**********************************************************************************/
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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module THEIACORE
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//---------------------------------------------------------------------------
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module THEIA
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(
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(
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input wire CLK_I, //Input clock
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input wire CLK_I, //Input clock
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input wire RST_I, //Input reset
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input wire RST_I, //Input reset
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//Theia Interfaces
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//Theia Interfaces
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input wire CYC_I, //Bus cycle signal, see wishbone documentation
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input wire CYC_I, //Bus cycle signal, see wishbone documentation
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output wire [1:0] TGC_O, //Bus cycle tag, see THEAI documentation
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output wire [1:0] TGC_O, //Bus cycle tag, see THEAI documentation
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input wire [1:0] TGA_I, //Input address tag, see THEAI documentation
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input wire [1:0] TGA_I, //Input address tag, see THEAI documentation
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output wire [1:0] TGA_O, //Output address tag, see THEAI documentation
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output wire [1:0] TGA_O, //Output address tag, see THEAI documentation
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input wire [1:0] TGC_I, //Bus cycle tag, see THEAI documentation
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input wire [1:0] TGC_I, //Bus cycle tag, see THEAI documentation
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input wire [`MAX_CORES-1:0] SEL_I, //The WishBone Master uses this signal to configure a specific core (TBD, not sure is needed)
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input wire [`MAX_CORES-1:0] RENDREN_I,
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//Control Register
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//Control Register
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input wire [15:0] CREG_I
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input wire [15:0] CREG_I,
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output wire DONE_O
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);
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);
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//Alias this signals
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wire Clock,Reset;
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assign Clock = CLK_I;
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assign Reset = RST_I;
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wire [`DATA_ROW_WIDTH-1:0] wEXE_2__MEM_WriteData;
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wire [`DATA_ROW_WIDTH-1:0] wUCODE_RAMBus;
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wire [`DATA_ADDRESS_WIDTH-1:0] wEXE_2__MEM_wDataWriteAddress;
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wire w2IO__AddrIsImm;
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wire [`DATA_ADDRESS_WIDTH-1:0] wUCODE_RAMAddress;
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wire [`DATA_ADDRESS_WIDTH-1:0] w2IO__Adr_O_Pointer;
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wire [`DATA_ADDRESS_WIDTH-1:0] wGEO2_IO__Adr_O_Pointer;
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wire wEXE_2__DataWriteEnable;
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wire wUCODE_RAMWriteEnable;
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wire [2:0] RamBusOwner;
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//Unit intercoanection wires
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wire wCU2__MicrocodeExecutionDone;
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wire [`ROM_ADDRESS_WIDTH-1:0] InitialCodeAddress;
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wire [`ROM_ADDRESS_WIDTH-1:0] wInstructionPointer1,wInstructionPointer2;
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wire [`INSTRUCTION_WIDTH-1:0] wEncodedInstruction1,wEncodedInstruction2,wIO2_MEM__ExternalInstruction;
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wire wCU2__ExecuteMicroCode;
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wire [`ROM_ADDRESS_WIDTH-1:0] wIO2_MEM__InstructionWriteAddr;
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wire [95:0] wMEM_2__EXE_DataRead0, wMEM_2__EXE_DataRead1,wMEM_2__IO_DataRead0, wMEM_2__IO_DataRead1;
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wire [`DATA_ADDRESS_WIDTH-1:0] wEXE_2__MEM_DataReadAddress0,wEXE_2__MEM_DataReadAddress1;
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wire [`DATA_ADDRESS_WIDTH-1:0] wUCODE_RAMReadAddress0,wUCODE_RAMReadAddress1;
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wire [`WIDTH-1:0] w2IO__AddressOffset;
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wire [`DATA_ADDRESS_WIDTH-1:0] w2IO__DataWriteAddress;
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wire w2IO__Store;
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wire w2IO__EnableWBMaster;
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wire [`DATA_ADDRESS_WIDTH-1:0] wIO2_MEM__DataWriteAddress;
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wire [`DATA_ADDRESS_WIDTH-1:0] wIO_2_MEM__DataReadAddress0;
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wire [`DATA_ROW_WIDTH-1:0] wIO2_MEM__Bus;
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wire [`WIDTH-1:0] wIO2_MEM__Data;
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wire [`WIDTH-1:0] wIO2_WBM__Address;
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wire wIO2_MEM__DataWriteEnable;
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wire wIO2__Done;
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wire wCU2_GEO__GeometryFetchEnable;
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wire wIFU2__MicroCodeReturnValue;
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wire wCU2_BCU__ACK;
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wire wGEO2_CU__RequestAABBIU;
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wire wGEO2_CU__RequestBIU;
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wire wGEO2_CU__RequestTCC;
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wire wGEO2_CU__GeometryUnitDone;
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wire wGEO2_CU__Sync;
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wire wEXE2__uCodeDone;
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wire wEXE2_IFU__EXEBusy;
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wire [`DATA_ADDRESS_WIDTH-1:0] wEXE2_IDU_DataFordward_LastDestination;
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wire wALU2_EXE__BranchTaken;
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wire wALU2_IFU_BranchNotTaken;
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wire w2IO__SetAddress;
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wire wIDU2_IFU__IDUBusy;
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//Control Registe wires
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wire[15:0] wCR2_ControlRegister;
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wire wCR2_TextureMappingEnabled;
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wire wGEO2_CU__TFFDone;
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wire wCU2_GEO__TriggerTFF;
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wire wIO2_MEM_InstructionWriteEnable;
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wire wCU2_IO__WritePixel;
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wire wGEO2_IO__AddrIsImm;
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wire[31:0] wGEO2_IO__AddressOffset;
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wire wGEO2_IO__EnableWBMaster;
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wire wGEO2_IO__SetAddress;
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wire[`WIDTH-1:0] wGEO2__CurrentPitch,wCU2_GEO_Pitch;
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wire wCU2_GEO__SetPitch,wCU2_GEO__IncPicth;
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wire wCU2_FlipMemEnabled;
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wire w2MEM_FlipMemory;
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`ifdef DEBUG
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wire [`ROM_ADDRESS_WIDTH-1:0] wDEBUG_IDU2_EXE_InstructionPointer;
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`endif
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//--------------------------------------------------------
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/*
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///////////////// TODO CHANGE FOR MUXES ////////////////////////////////
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assign wEXE_2__MEM_WriteData = ( RamBusOwner == `REG_BUS_OWNED_BY_UCODE ) ?
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wUCODE_RAMBus : `DATA_ROW_WIDTH'bz;
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assign wEXE_2__MEM_WriteData = ( RamBusOwner == `REG_BUS_OWNED_BY_GFU || MST_I == 1'b1) ?
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wIO2_MEM__Bus : `DATA_ROW_WIDTH'bz;
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assign wEXE_2__MEM_wDataWriteAddress = ( RamBusOwner == `REG_BUS_OWNED_BY_UCODE ) ?
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wUCODE_RAMAddress : `DATA_ADDRESS_WIDTH'bz;
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assign wEXE_2__MEM_wDataWriteAddress = ( RamBusOwner == `REG_BUS_OWNED_BY_GFU || MST_I == 1'b1) ?
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wIO2_MEM__DataWriteAddress : `DATA_ADDRESS_WIDTH'bz;
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MUXFULLPARALELL_2SEL_GENERIC # ( `DATA_ADDRESS_WIDTH ) MUX_RA0
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(
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.Sel(RamBusOwner[1:0]),
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.I1(`DATA_ADDRESS_WIDTH'b0),
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.I2(wIO_2_MEM__DataReadAddress0),
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.I3(wUCODE_RAMReadAddress0),
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.O1(wEXE_2__MEM_DataReadAddress0)
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);
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wire [`MAX_CORES-1:0] wDone;
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wire [`MAX_CORES-1:0] wBusGranted,wBusRequest;
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wire [`WB_WIDTH-1:0] wDAT_O_0,wDAT_O_1,wDAT_O_2,wDAT_O_3;
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wire [`WB_WIDTH-1:0] wADR_O_0,wADR_O_1,wADR_O_2,wADR_O_3;
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wire [1:0] wTGA_O_0,wTGA_O_1,wTGA_O_2,wTGA_O_3;
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wire [1:0] wBusSelect;
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//wire wSTB_O_0,wSTB_O_1,wSTB_O_2,wSTB_O_3;
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//wire wWE_O_0,wWE_O_1,wWE_O_2,wWE_O_3;
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wire [`MAX_CORES-1:0] wSTB_O,wWE_O;
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wire wACK_O_0,wACK_O_1,wACK_O_2,wACK_O_3;
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wire [`MAX_CORES-1:0] wSTB_I;
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wire [`MAX_CORES-1:0] wMST_I;
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wire [`MAX_CORES-1:0] wACK_I;
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wire [`MAX_CORES-1:0] wCYC_I;
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wire [1:0] wTGA_I[`MAX_CORES-1:0];
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assign wEXE_2__DataWriteEnable = ( RamBusOwner == `REG_BUS_OWNED_BY_UCODE && MST_I == 1'b0) ?
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//assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3];
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wUCODE_RAMWriteEnable : 1'bz;
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//assign DONE_O = wDone[1];
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assign DONE_O = wDone[0] & wDone[1];
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assign wEXE_2__DataWriteEnable = ( RamBusOwner == `REG_BUS_OWNED_BY_GFU || MST_I == 1'b1) ?
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//----------------------------------------------------------------
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wIO2_MEM__DataWriteEnable : 1'bz;
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// assign wDone[3:1] = 3'b111;
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*/
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assign wBusRequest[3:2] = 0;
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assign wCR2_TextureMappingEnabled = wCR2_ControlRegister[ `CR_EN_TEXTURE ];
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assign wSTB_O[3:2] = 0;
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wire wCU2_FlipMem;
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assign wWE_O[3:2] = 0;
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//--------------------------------------------------------
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Module_BusArbitrer ARB1
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//Control Unit Instance
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ControlUnit CU
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(
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(
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.Clock(Clock),
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.Clock( CLK_I ),
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.Reset(Reset),
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.Reset( RST_I ),
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.oFlipMemEnabled( wCU2_FlipMemEnabled ),
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.iRequest( wBusRequest ),
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.oFlipMem( wCU2_FlipMem ),
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.oGrant( wBusGranted ),
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.iControlRegister( wCR2_ControlRegister ),
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.oBusSelect( wBusSelect )
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.oRamBusOwner( RamBusOwner ),
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.oGFUEnable( wCU2_GEO__GeometryFetchEnable ),
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.iTriggerAABBIURequest( wGEO2_CU__RequestAABBIU ),
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.iTriggerBIURequest( wGEO2_CU__RequestBIU ),
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.iTriggertTCCRequest( wGEO2_CU__RequestTCC ),
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.oUCodeEnable( wCU2__ExecuteMicroCode ),
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.oCodeInstructioPointer( InitialCodeAddress ),
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.iUCodeDone( wCU2__MicrocodeExecutionDone ),
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.iIODone( wIO2__Done ),
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.oIOWritePixel( wCU2_IO__WritePixel ),
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.iUCodeReturnValue( wIFU2__MicroCodeReturnValue ),
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.iGEOSync( wGEO2_CU__Sync ),
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.iTFFDone( wGEO2_CU__TFFDone ),
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.oTriggerTFF( wCU2_GEO__TriggerTFF ),
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.MST_I( MST_I ),
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.oSetCurrentPitch( wCU2_GEO__SetPitch ),
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.iGFUDone( wGEO2_CU__GeometryUnitDone )
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);
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);
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//----------------------------------------------------------------
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//The Muxes
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//DAT_O Mux
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MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX_DAT_O
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//--------------------------------------------------------
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//assign w2MEM_FlipMemory = (wCU2__ExecuteMicroCode | wCU2_FlipMem ) & wCU2_FlipMemEnabled;
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assign w2MEM_FlipMemory = wCU2_FlipMem & wCU2_FlipMemEnabled;
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MemoryUnit MEM
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(
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(
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.Clock(Clock),
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.Sel(wBusSelect),
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.Reset(Reset),
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.I1(wDAT_O_0),
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.I2(wDAT_O_1),
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.iFlipMemory( w2MEM_FlipMemory ),
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.I3(wDAT_O_2),
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.I4(wDAT_O_3),
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//Data Bus to/from EXE
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.O1( DAT_O )
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.iDataReadAddress1_EXE( wEXE_2__MEM_DataReadAddress0 ),
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);
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.iDataReadAddress2_EXE( wEXE_2__MEM_DataReadAddress1 ),
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.oData1_EXE( wMEM_2__EXE_DataRead0 ),
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.oData2_EXE( wMEM_2__EXE_DataRead1 ),
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.iDataWriteEnable_EXE( wEXE_2__DataWriteEnable ),
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.iDataWriteAddress_EXE( wEXE_2__MEM_wDataWriteAddress ),
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.iData_EXE( wEXE_2__MEM_WriteData ),
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//Data Bus to/from IO
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.iDataReadAddress1_IO( wIO_2_MEM__DataReadAddress0 ),
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.iDataReadAddress2_IO( wIO_2_MEM__DataReadAddress1 ),
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.oData1_IO( wMEM_2__IO_DataRead0 ),
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.oData2_IO( wMEM_2__IO_DataRead1 ),
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.iDataWriteEnable_IO( wIO2_MEM__DataWriteEnable ),
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.iDataWriteAddress_IO( wIO2_MEM__DataWriteAddress ),
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.iData_IO( wIO2_MEM__Bus ),
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//Instruction Bus
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.iInstructionReadAddress1( wInstructionPointer1 ),
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.iInstructionReadAddress2( wInstructionPointer2 ),
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.oInstruction1( wEncodedInstruction1 ),
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.oInstruction2( wEncodedInstruction2 ),
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.iInstructionWriteEnable( wIO2_MEM_InstructionWriteEnable ),
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.iInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr ),
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.iInstruction( wIO2_MEM__ExternalInstruction ),
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.iControlRegister( CREG_I ),
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.oControlRegister( wCR2_ControlRegister )
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MUXFULLPARALELL_2SEL_GENERIC # ( `WB_WIDTH ) MUX_ADR_O
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(
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.Sel(wBusSelect),
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.I1(wADR_O_0),
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.I2(wADR_O_1),
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.I3(wADR_O_2),
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.I4(wADR_O_3),
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.O1( ADR_O )
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);
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);
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////--------------------------------------------------------
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ExecutionUnit EXE
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MUXFULLPARALELL_2SEL_GENERIC # ( 1 ) MUX_STB_O
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(
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(
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.Sel(wBusSelect),
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.I1(wSTB_O[0]),
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.I2(wSTB_O[1]),
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.I3(wSTB_O[2]),
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.I4(wSTB_O[3]),
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.O1( STB_O )
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);
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.Clock( Clock),
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.Reset( Reset ),
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.iInitialCodeAddress( InitialCodeAddress ),
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.iInstruction1( wEncodedInstruction1 ),
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.iInstruction2( wEncodedInstruction2 ),
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.oInstructionPointer1( wInstructionPointer1 ),
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.oInstructionPointer2( wInstructionPointer2 ),
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.iDataRead0( wMEM_2__EXE_DataRead0 ),
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.iDataRead1( wMEM_2__EXE_DataRead1 ),
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.iTrigger( wCU2__ExecuteMicroCode ),
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.oDataReadAddress0( wEXE_2__MEM_DataReadAddress0 ),
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.oDataReadAddress1( wEXE_2__MEM_DataReadAddress1 ),
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.oDataWriteEnable( wEXE_2__DataWriteEnable ),
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.oDataWriteAddress( wEXE_2__MEM_wDataWriteAddress ),
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.oDataBus( wEXE_2__MEM_WriteData ),
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.oReturnCode( wIFU2__MicroCodeReturnValue ),
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.oDone( wCU2__MicrocodeExecutionDone )
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MUXFULLPARALELL_2SEL_GENERIC # ( 1 ) MUX_WE_O
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(
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.Sel(wBusSelect),
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.I1(wWE_O[0]),
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.I2(wWE_O[1]),
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.I3(wWE_O[2]),
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.I4(wWE_O[3]),
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.O1( WE_O )
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);
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);
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////--------------------------------------------------------
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wire wGEO2__RequestingTextures;
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wire w2IO_WriteBack_Set;
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GeometryUnit GEO
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MUXFULLPARALELL_2SEL_GENERIC # ( 2 ) MUX_TGA_O
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(
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(
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.Clock( Clock ),
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.Sel(wBusSelect),
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.Reset( Reset ),
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.I1(wTGA_O_0),
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.iEnable( wCU2_GEO__GeometryFetchEnable ),
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.I2(wTGA_O_1),
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.iTexturingEnable( wCR2_TextureMappingEnabled ),
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.I3(wTGA_O_2),
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//Wires from IO
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.I4(wTGA_O_3),
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.iData_WBM( wIO2_MEM__Data ),
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.O1( TGA_O )
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.iDataReady_WBM( wIO2__Done ),
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//Wires to WBM
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.oAddressWBM_Imm( wGEO2_IO__AddressOffset ),
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.oAddressWBM_fromMEM( wGEO2_IO__Adr_O_Pointer ),
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.oAddressWBM_IsImm( wGEO2_IO__AddrIsImm ),
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.oEnable_WBM( wGEO2_IO__EnableWBMaster ),
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.oSetAddressWBM( wGEO2_IO__SetAddress ),
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.oSetIOWriteBackAddr( w2IO_WriteBack_Set ),
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//Wires to CU
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.oRequest_AABBIU( wGEO2_CU__RequestAABBIU ),
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.oRequest_BIU( wGEO2_CU__RequestBIU ),
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.oRequest_TCC( wGEO2_CU__RequestTCC ),
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.oTFFDone( wGEO2_CU__TFFDone ),
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//Wires to RAM-Bus MUX
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.oRAMWriteAddress( w2IO__DataWriteAddress ),
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.oRAMWriteEnable( w2IO__Store ),
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//Wires from Execution Unit
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.iMicrocodeExecutionDone( wCU2__MicrocodeExecutionDone ),
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.iMicroCodeReturnValue( wIFU2__MicroCodeReturnValue ),
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.oSync( wGEO2_CU__Sync ),
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.iTrigger_TFF( wCU2_GEO__TriggerTFF ),
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.iBIUHit( wIFU2__MicroCodeReturnValue ),
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.oRequestingTextures( wGEO2__RequestingTextures ),
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.oDone( wGEO2_CU__GeometryUnitDone )
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);
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);
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assign TGA_O = (wGEO2__RequestingTextures) ? 2'b1: 2'b0;
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assign ACK_O = (wACK_O_0 | wACK_O_1);// | wACK_O_2 | wACK_O_3);
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//---------------------------------------------------------------------------------------------------
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wire[`DATA_ADDRESS_WIDTH-1:0] wIO_2_MEM__DataReadAddress1;
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assign wEXE_2__MEM_DataReadAddress1 = (wCU2_IO__WritePixel == 0) ? wUCODE_RAMReadAddress1 : wIO_2_MEM__DataReadAddress1;
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assign w2IO__EnableWBMaster = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__EnableWBMaster : wCU2_IO__WritePixel;
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assign w2IO__AddrIsImm = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddrIsImm : 1'b1;
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assign w2IO__AddressOffset = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__AddressOffset : 32'b0;
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assign w2IO__Adr_O_Pointer = (wCU2_IO__WritePixel == 0 ) ? wGEO2_IO__Adr_O_Pointer : `OREG_PIXEL_PITCH;
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wire w2IO_MasterCycleType;
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assign w2IO_MasterCycleType = (wCU2_IO__WritePixel) ? `WB_SIMPLE_WRITE_CYCLE : `WB_SIMPLE_READ_CYCLE;
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assign wMST_I[0] = (SEL_I[0]) ? MST_I : 0;
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assign wMST_I[1] = (SEL_I[1]) ? MST_I : 0;
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assign wMST_I[2] = (SEL_I[2]) ? MST_I : 0;
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assign wMST_I[3] = (SEL_I[3]) ? MST_I : 0;
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assign wSTB_I[0] = (SEL_I[0]) ? STB_I : 0;
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assign wSTB_I[1] = (SEL_I[1]) ? STB_I : 0;
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assign wSTB_I[2] = (SEL_I[2]) ? STB_I : 0;
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assign wSTB_I[3] = (SEL_I[3]) ? STB_I : 0;
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assign w2IO__SetAddress = (wCU2_IO__WritePixel == 0 )? wGEO2_IO__SetAddress : wCU2_GEO__SetPitch;
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assign wCYC_I[0] = (SEL_I[0]) ? CYC_I : 0;
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assign wCYC_I[1] = (SEL_I[1]) ? CYC_I : 0;
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assign wCYC_I[2] = (SEL_I[2]) ? CYC_I : 0;
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assign wCYC_I[3] = (SEL_I[3]) ? CYC_I : 0;
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assign wTGA_I[0] = (SEL_I[0]) ? TGA_I : 0;
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assign wTGA_I[1] = (SEL_I[1]) ? TGA_I : 0;
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assign wTGA_I[2] = (SEL_I[2]) ? TGA_I : 0;
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assign wTGA_I[3] = (SEL_I[3]) ? TGA_I : 0;
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IO_Unit IO
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//----------------------------------------------------------------
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|
wire foo;
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assign foo = ACK_I;
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THEIACORE THEIA_CORE0
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(
|
(
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.Clock( Clock ),
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.CLK_I( CLK_I ),
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.Reset( Reset ),
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.RST_I( RST_I ),
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.iEnable( w2IO__EnableWBMaster ),
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.RENDREN_I( RENDREN_I[0] ),
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.iBusCyc_Type( w2IO_MasterCycleType ),
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|
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.iStore( w2IO__Store ),
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.iAdr_DataWriteBack( w2IO__DataWriteAddress ),
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.iAdr_O_Set( w2IO__SetAddress ),
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.iAdr_O_Imm( w2IO__AddressOffset ),
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.iAdr_O_Type( w2IO__AddrIsImm ),
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.iAdr_O_Pointer( w2IO__Adr_O_Pointer ),
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.iReadDataBus( wMEM_2__IO_DataRead0 ),
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.iReadDataBus2( wMEM_2__IO_DataRead1 ),
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.iDat_O_Pointer( `OREG_PIXEL_COLOR ),
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|
|
|
|
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.oDataReadAddress( wIO_2_MEM__DataReadAddress0 ),
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.oDataReadAddress2( wIO_2_MEM__DataReadAddress1 ),
|
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.oDataWriteAddress( wIO2_MEM__DataWriteAddress ),
|
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.oDataBus( wIO2_MEM__Bus ),
|
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.oInstructionBus( wIO2_MEM__ExternalInstruction ),
|
|
|
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.oDataWriteEnable( wIO2_MEM__DataWriteEnable ),
|
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.oData( wIO2_MEM__Data ),
|
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.oInstructionWriteEnable( wIO2_MEM_InstructionWriteEnable ),
|
|
.oInstructionWriteAddress( wIO2_MEM__InstructionWriteAddr ),
|
|
.iWriteBack_Set( w2IO_WriteBack_Set ),
|
|
|
|
.oDone( wIO2__Done ),
|
//Slave signals
|
.MST_I( MST_I ),
|
|
//Wish Bone Interface
|
|
.DAT_I( DAT_I ),
|
|
.DAT_O( DAT_O ),
|
|
.ACK_I( ACK_I ),
|
|
.ACK_O( ACK_O ),
|
|
.ADR_O( ADR_O ),
|
|
.ADR_I( ADR_I ),
|
.ADR_I( ADR_I ),
|
.WE_O( WE_O ),
|
|
.WE_I( WE_I ),
|
.WE_I( WE_I ),
|
.STB_O( STB_O ),
|
.STB_I( wSTB_I[0] ),
|
.STB_I( STB_I ),
|
//-----------------------------------
|
.CYC_O( CYC_O ),
|
//This signal behaves in a very funny way...
|
.TGA_I( TGA_I ),
|
//
|
.CYC_I( CYC_I ),
|
.ACK_I( ACK_I ),//& wBusGranted[0] ),//wACK_I[0] ), //WTF??? ok I think it works fine like this...
|
.TGC_O( TGC_O )
|
//-----------------------------------
|
|
.CYC_I( wCYC_I[0] ),
|
|
.MST_I( wMST_I[0] ),
|
|
.TGA_I( wTGA_I[0] ),
|
|
.CREG_I( CREG_I ),
|
|
|
|
//Master Signals
|
|
.WE_O ( wWE_O[0] ),
|
|
.STB_O( wSTB_O[0] ),
|
|
.ACK_O( wACK_O_0 ),
|
|
.DAT_O( wDAT_O_0 ),
|
|
.ADR_O( wADR_O_0 ),
|
|
.CYC_O( wBusRequest[0] ),
|
|
.GNT_I( wBusGranted[0] ),
|
|
.TGA_O( wTGA_O_0 ),
|
|
`ifdef DEBUG
|
|
.iDebug_CoreID( `MAX_CORES'd0 ),
|
|
`endif
|
|
//Other
|
|
.DAT_I( DAT_I ),
|
|
.DONE_O( wDone[0] )
|
|
|
|
);
|
|
//----------------------------------------------------------------
|
|
THEIACORE THEIA_CORE1
|
|
(
|
|
.CLK_I( CLK_I ),
|
|
.RST_I( RST_I ),
|
|
.RENDREN_I( RENDREN_I[1] ),
|
|
|
|
//Slave signals
|
|
.ADR_I( ADR_I ),
|
|
.WE_I( WE_I ),
|
|
.STB_I( wSTB_I[1] ),//ok
|
|
.ACK_I( ACK_I ),//& wBusGranted[1] ),//wACK_I[0] ), //WTF??? ok I think it works fine like this...
|
|
.CYC_I( wCYC_I[1] ),//ok
|
|
.MST_I( wMST_I[1] ),//ok
|
|
.TGA_I( wTGA_I[1] ),//ok
|
|
.CREG_I( CREG_I ),
|
|
|
|
//Master Signals
|
|
.WE_O ( wWE_O[1] ),
|
|
.STB_O( wSTB_O[1] ),
|
|
.ACK_O( wACK_O_1 ),
|
|
.DAT_O( wDAT_O_1 ),
|
|
.ADR_O( wADR_O_1 ),
|
|
.CYC_O( wBusRequest[1] ),
|
|
.GNT_I( wBusGranted[1] ),
|
|
.TGA_O( wTGA_O_1 ),
|
|
`ifdef DEBUG
|
|
.iDebug_CoreID( `MAX_CORES'd1 ),
|
|
`endif
|
|
//Other
|
|
.DAT_I( DAT_I ),
|
|
.DONE_O( wDone[1] )
|
|
|
);
|
);
|
//---------------------------------------------------------------------------------------------------
|
//----------------------------------------------------------------
|
|
|
|
|
endmodule
|
endmodule
|
|
//---------------------------------------------------------------------------
|
|
|
No newline at end of file
|
No newline at end of file
|
