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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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//------------------------------------------------
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module FFD_POSEDGE_ASYNC_RESET # ( parameter SIZE=`WIDTH )
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(
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input wire Clock,
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input wire Clear,
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input wire [SIZE-1:0] D,
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output reg [SIZE-1:0] Q
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);
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always @(posedge Clock or posedge Clear)
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begin
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if (Clear)
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Q = 0;
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else
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Q = D;
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end
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endmodule
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//----------------------------------------------------
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module FFD_POSEDGE_SYNCRONOUS_RESET # ( parameter SIZE=`WIDTH )
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(
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input wire Clock,
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input wire Reset,
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input wire Enable,
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input wire [SIZE-1:0] D,
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output reg [SIZE-1:0] Q
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);
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always @ (posedge Clock)
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begin
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if ( Reset )
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Q <= `WIDTH'b0;
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else
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begin
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if (Enable)
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Q <= D;
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end
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end//always
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endmodule
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//------------------------------------------------
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module UPCOUNTER_POSEDGE # (parameter SIZE=`WIDTH)
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(
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input wire Clock, Reset,
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input wire [SIZE-1:0] Initial,
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input wire Enable,
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output reg [SIZE-1:0] Q
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);
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always @(posedge Clock )
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begin
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if (Reset)
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Q <= Initial;
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else
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begin
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if (Enable)
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Q <= Q + 1;
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end
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end
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endmodule
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//----------------------------------------------------------------------
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module SELECT_1_TO_N # ( parameter SEL_WIDTH=4, parameter OUTPUT_WIDTH=16 )
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(
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input wire [SEL_WIDTH-1:0] Sel,
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input wire En,
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output wire [OUTPUT_WIDTH-1:0] O
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);
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reg[OUTPUT_WIDTH-1:0] shift;
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always @ ( * )
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begin
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if (~En)
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shift = 1;
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else
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shift = (1 << Sel);
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end
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assign O = ( ~En ) ? 0 : shift ;
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//assign O = En & (1 << Sel);
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endmodule
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//----------------------------------------------------------------------
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module MUXFULLPARALELL_2SEL_GENERIC # ( parameter SIZE=`WIDTH )
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(
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input wire [1:0] Sel,
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input wire [SIZE-1:0]I1, I2, I3,I4,
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output reg [SIZE-1:0] O1
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);
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always @( * )
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begin
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case (Sel)
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2'b00: O1 = I1;
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2'b01: O1 = I2;
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2'b10: O1 = I3;
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2'b11: O1 = I4;
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default: O1 = SIZE-1'b0;
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endcase
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end
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endmodule
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//--------
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module CIRCULAR_SHIFTLEFT_POSEDGE_EX # ( parameter SIZE=`WIDTH )
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( input wire Clock,
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input wire Reset,
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input wire[SIZE-1:0] Initial,
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input wire Enable,
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output wire[SIZE-1:0] O
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);
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reg [SIZE-1:0] tmp;
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always @(posedge Clock)
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begin
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if (Reset)
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tmp <= Initial;
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else
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begin
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if (Enable)
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begin
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if (tmp[SIZE-1])
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begin
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tmp <= Initial;
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end
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else
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begin
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tmp <= tmp << 1;
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end
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end
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end
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end
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assign O = tmp;
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endmodule
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//------------------------------------------------
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module MUXFULLPARALELL_3SEL_WALKINGONE # ( parameter SIZE=`WIDTH )
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(
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input wire [2:0] Sel,
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input wire [SIZE-1:0]I1, I2, I3,
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output reg [SIZE-1:0] O1
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);
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always @( * )
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begin
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case (Sel)
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3'b001: O1 = I1;
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3'b010: O1 = I2;
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3'b100: O1 = I3;
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default: O1 = SIZE-1'b0;
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endcase
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end
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endmodule
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//------------------------------------------------
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module SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
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( input wire Clock,
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input wire Reset,
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input wire[SIZE-1:0] Initial,
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input wire Enable,
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output wire[SIZE-1:0] O
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);
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reg [SIZE-1:0] tmp;
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always @(posedge Clock)
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begin
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if (Reset)
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tmp <= Initial;
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else
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begin
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if (Enable)
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tmp <= tmp << 1;
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end
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end
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assign O = tmp;
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endmodule
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//------------------------------------------------
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//------------------------------------------------
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module CIRCULAR_SHIFTLEFT_POSEDGE # ( parameter SIZE=`WIDTH )
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( input wire Clock,
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input wire Reset,
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input wire[SIZE-1:0] Initial,
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input wire Enable,
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output wire[SIZE-1:0] O
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);
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reg [SIZE-1:0] tmp;
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always @(posedge Clock)
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begin
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if (Reset || tmp[SIZE-1])
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tmp <= Initial;
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else
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begin
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if (Enable)
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tmp <= tmp << 1;
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end
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end
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assign O = tmp;
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endmodule
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//-----------------------------------------------------------
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/*
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Sorry forgot how this flop is called.
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Any way Truth table is this
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Q S Q_next R
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0 0 0 0
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0 1 1 0
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1 0 1 0
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1 1 1 0
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X X 0 1
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The idea is that it toggles from 0 to 1 when S = 1, but if it
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gets another S = 1, it keeps the output to 1.
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*/
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module FFToggleOnce_1Bit
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(
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input wire Clock,
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input wire Reset,
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input wire Enable,
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input wire S,
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output reg Q
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);
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reg Q_next;
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always @ (negedge Clock)
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begin
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Q <= Q_next;
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end
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always @ ( posedge Clock )
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begin
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if (Reset)
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Q_next <= 0;
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else if (Enable)
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Q_next <= (S && !Q) || Q;
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else
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Q_next <= Q;
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end
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endmodule
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//-----------------------------------------------------------
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module UpCounter_16E
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(
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input wire Clock,
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input wire Reset,
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input wire [15:0] Initial,
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input wire Enable,
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output wire [15:0] Q
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);
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reg [15:0] Temp;
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always @(posedge Clock or posedge Reset)
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begin
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if (Reset)
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Temp = Initial;
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else
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if (Enable)
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Temp = Temp + 1'b1;
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end
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assign Q = Temp;
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endmodule
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//-----------------------------------------------------------
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module UpCounter_32
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(
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input wire Clock,
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input wire Reset,
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input wire [31:0] Initial,
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input wire Enable,
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output wire [31:0] Q
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);
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reg [31:0] Temp;
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always @(posedge Clock or posedge Reset)
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begin
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if (Reset)
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begin
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Temp = Initial;
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end
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else
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begin
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if (Enable)
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begin
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Temp = Temp + 1'b1;
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end
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end
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end
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assign Q = Temp;
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endmodule
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//-----------------------------------------------------------
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module UpCounter_3
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(
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input wire Clock,
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input wire Reset,
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input wire [2:0] Initial,
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input wire Enable,
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output wire [2:0] Q
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);
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reg [2:0] Temp;
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always @(posedge Clock or posedge Reset)
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begin
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if (Reset)
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Temp = Initial;
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else
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if (Enable)
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Temp = Temp + 3'b1;
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end
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assign Q = Temp;
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endmodule
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module FFD32_POSEDGE
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(
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input wire Clock,
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input wire[31:0] D,
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output reg[31:0] Q
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);
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always @ (posedge Clock)
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Q <= D;
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endmodule
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//------------------------------------------------
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module MUXFULLPARALELL_96bits_2SEL
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(
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input wire Sel,
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input wire [95:0]I1, I2,
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output reg [95:0] O1
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);
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always @( * )
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begin
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case (Sel)
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1'b0: O1 = I1;
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1'b1: O1 = I2;
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endcase
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end
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endmodule
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//------------------------------------------------
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module MUXFULLPARALELL_16bits_2SEL_X
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(
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input wire [1:0] Sel,
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input wire [15:0]I1, I2, I3,
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output reg [15:0] O1
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);
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always @( * )
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begin
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case (Sel)
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2'b00: O1 = I1;
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2'b01: O1 = I2;
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2'b10: O1 = I3;
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default: O1 = 16'b0;
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endcase
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end
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endmodule
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//------------------------------------------------
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module MUXFULLPARALELL_16bits_2SEL
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(
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input wire Sel,
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input wire [15:0]I1, I2,
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output reg [15:0] O1
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);
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always @( * )
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begin
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case (Sel)
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1'b0: O1 = I1;
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1'b1: O1 = I2;
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endcase
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end
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endmodule
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//--------------------------------------------------------------
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module FFT1
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(
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input wire D,
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input wire Clock,
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input wire Reset ,
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output reg Q
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);
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always @ ( posedge Clock or posedge Reset )
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begin
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if (Reset)
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begin
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Q <= 1'b0;
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end
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else
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begin
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if (D)
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Q <= ! Q;
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end
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end//always
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endmodule
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//--------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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