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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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`define EXEU_AFTER_RESET 0
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`define EXEU_INITIAL_STATE 1
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`define EXEU_WAIT_FOR_DECODE 2
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`define EXEU_FETCH_DECODED_INST 3
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`define EXEU_WAIT_FOR_ALU_EXECUTION 4
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`define EXEU_WRITE_BACK_TO_RAM 5
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`define EXEU_HANDLE_JUMP 7
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module ExecutionFSM
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(
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input wire Clock,
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input wire Reset,
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input wire iDecodeDone,
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input wire[`INSTRUCTION_OP_LENGTH-1:0] iOperation,
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input wire[`DATA_ROW_WIDTH-1:0] iSource0,iSource1,
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input wire[`DATA_ADDRESS_WIDTH-1:0] iDestination,
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inout wire[`DATA_ROW_WIDTH-1:0] RAMBus,
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//output reg ReadyForNextInstruction,
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output wire oJumpFlag ,
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output wire [`ROM_ADDRESS_WIDTH-1:0] oJumpIp ,
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output wire oRAMWriteEnable ,
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output wire [`DATA_ADDRESS_WIDTH-1:0] oRAMWriteAddress ,
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output wire oExeLatchedValues,
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output reg oBusy ,
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//ALU ports and control signals
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output wire [`INSTRUCTION_OP_LENGTH-1:0] oALUOperation,
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output wire [`WIDTH-1:0] oALUChannelX1,
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output wire [`WIDTH-1:0] oALUChannelY1,
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output wire [`WIDTH-1:0] oALUChannelZ1,
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output wire [`WIDTH-1:0] oALUChannelX2,
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output wire [`WIDTH-1:0] oALUChannelY2,
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output wire [`WIDTH-1:0] oALUChannelZ2,
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output wire oTriggerALU,
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input wire [`WIDTH-1:0] iALUResultX,
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input wire [`WIDTH-1:0] iALUResultY,
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input wire [`WIDTH-1:0] iALUResultZ,
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input wire iALUOutputReady,
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input wire iBranchTaken,
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input wire iBranchNotTaken,
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`ifdef DEBUG
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input wire[`ROM_ADDRESS_WIDTH-1:0] iDebug_CurrentIP,
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input wire [`MAX_CORES-1:0] iDebug_CoreID,
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`endif
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//Data forward Signals
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output wire [`DATA_ADDRESS_WIDTH-1:0] oLastDestination
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);
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wire wLatchNow;
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reg rInputLatchesEnabled;
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//If ALU says jump, just pass along
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assign oJumpFlag = iBranchTaken;
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//JumpIP is the instruction destination (= oRAMWriteAddress)
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assign oJumpIp = oRAMWriteAddress;
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assign wLatchNow = iDecodeDone & rInputLatchesEnabled;
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assign oExeLatchedValues = wLatchNow;
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assign oTriggerALU = wLatchNow;
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wire wOperationIsJump;
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assign wOperationIsJump = iBranchTaken || iBranchNotTaken;
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//Don't allow me to write back back if the operation is a NOP
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`ifdef DEBUG
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assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump &&
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(oALUOperation != `NOP) && oALUOperation != `DEBUG_PRINT;
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`else
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assign oRAMWriteEnable = iALUOutputReady && !wOperationIsJump && oALUOperation != `NOP;
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`endif
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assign RAMBus = ( oRAMWriteEnable ) ? {iALUResultX,iALUResultY,iALUResultZ} : `DATA_ROW_WIDTH'bz;
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assign oALUChannelX1 = iSource1[95:64];
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assign oALUChannelY1 = iSource1[63:32];
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assign oALUChannelZ1 = iSource1[31:0];
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assign oALUChannelX2 = iSource0[95:64];
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assign oALUChannelY2 = iSource0[63:32];
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assign oALUChannelZ2 = iSource0[31:0];
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/*
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FF32_POSEDGE_SYNCRONOUS_RESET SourceX1
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(
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.D( iSource1[95:64] ),
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.Q( oALUChannelX1 )
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);
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FF32_POSEDGE_SYNCRONOUS_RESET SourceY1
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(
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.D( iSource1[63:32] ),
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.Q( oALUChannelY1 )
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);
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FF32_POSEDGE_SYNCRONOUS_RESET SourceZ1
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(
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.D( iSource1[31:0] ),
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.Q( oALUChannelZ1 )
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);
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*/
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/*
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
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(
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iSource1[95:64] ),
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.Q(oALUChannelX1)
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
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(
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iSource1[63:32] ),
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.Q(oALUChannelY1)
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
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(
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iSource1[31:0] ),
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.Q(oALUChannelZ1)
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);
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*/
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/*
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FF32_POSEDGE_SYNCRONOUS_RESET SourceX2
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(
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.D( iSource0[95:64] ),
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.Q( oALUChannelX2 )
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);
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FF32_POSEDGE_SYNCRONOUS_RESET SourceY2
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(
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.D( iSource0[63:32] ),
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.Q( oALUChannelY2 )
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);
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FF32_POSEDGE_SYNCRONOUS_RESET SourceZ2
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(
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.D( iSource0[31:0] ),
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.Q( oALUChannelZ2 )
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);
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*/
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/*
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
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(
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iSource0[95:64] ),
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.Q(oALUChannelX2)
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
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(
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iSource0[63:32] ),
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.Q(oALUChannelY2)
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
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(
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iSource0[31:0] ),
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.Q(oALUChannelZ2)
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);
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*/
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//Finally one more latch to store
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//the iOperation and the destination
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assign oALUOperation = iOperation;
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//assign oRAMWriteAddress = iDestination;
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/*
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FF_OPCODE_POSEDGE_SYNCRONOUS_RESET FFOperation
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(
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.D( iOperation ),
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.Q( oALUOperation )
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);
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FF16_POSEDGE_SYNCRONOUS_RESET PSRegDestination
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(
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.Clock( wLatchNow ),
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.Clear( Reset ),
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.D( iDestination ),
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.Q( oRAMWriteAddress )
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);
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*/
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/*
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `INSTRUCTION_OP_LENGTH ) FFOperation
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(
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iOperation ),
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.Q(oALUOperation)
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);
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*/
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `DATA_ADDRESS_WIDTH ) PSRegDestination
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(
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.Clock( Clock ),//wLatchNow ),
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.Reset( Reset),
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.Enable( wLatchNow ),//1'b1 ),
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.D( iDestination ),
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.Q(oRAMWriteAddress)
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);
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//Data forwarding
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assign oLastDestination = oRAMWriteAddress;
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reg [7:0] CurrentState;
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reg [7:0] NextState;
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//------------------------------------------------
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always @(posedge Clock or posedge Reset)
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begin
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if (Reset)
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CurrentState <= `EXEU_AFTER_RESET;
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else
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CurrentState <= NextState;
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end
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//------------------------------------------------
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always @( * )
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begin
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case (CurrentState)
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//------------------------------------------
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`EXEU_AFTER_RESET:
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begin
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//ReadyForNextInstruction <= 1;
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oBusy <= 0;
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rInputLatchesEnabled <= 1;
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NextState <= `EXEU_WAIT_FOR_DECODE;
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end
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//------------------------------------------
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/**
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At the same time iDecodeDone goes to 1, our Flops
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will store the value, so next clock cycle we can
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tell IDU to go ahead and decode the next instruction
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in the pipeline.
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*/
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`EXEU_WAIT_FOR_DECODE:
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begin
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//ReadyForNextInstruction <= 1;
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oBusy <= 0;
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rInputLatchesEnabled <= 1;
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if ( iDecodeDone ) //This same thing triggers the ALU
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NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
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else
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NextState <= `EXEU_WAIT_FOR_DECODE;
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end
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//------------------------------------------
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/*
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If the instruction is aritmetic then pass the parameters
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the ALU, else if it store iOperation then...
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*/
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`EXEU_WAIT_FOR_ALU_EXECUTION:
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begin
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//ReadyForNextInstruction <= 0; //*
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oBusy <= 1;
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rInputLatchesEnabled <= 0; //NO INTERRUPTIONS WHILE WE WAIT!!
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if ( iALUOutputReady ) /////This same thing enables writing th results to RAM
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NextState <= `EXEU_WAIT_FOR_DECODE;
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else
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NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
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end
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//------------------------------------------
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`EXEU_WRITE_BACK_TO_RAM:
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begin
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//ReadyForNextInstruction <= 0;
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oBusy <= 1;
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rInputLatchesEnabled <= 1;
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if ( iDecodeDone )
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NextState <= `EXEU_WAIT_FOR_ALU_EXECUTION;
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else
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NextState <= `EXEU_WAIT_FOR_DECODE;
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end
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//------------------------------------------
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default:
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begin
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//ReadyForNextInstruction <= 1;
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oBusy <= 0;
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rInputLatchesEnabled <= 1;
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NextState <= `EXEU_AFTER_RESET;
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end
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//------------------------------------------
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endcase
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end
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//-----------------------------------------------------------------------
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`ifdef DUMP_CODE
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integer ucode_file;
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integer reg_log;
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initial
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begin
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$display("Opening ucode dump file....\n");
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ucode_file = $fopen("Code.log","w");
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$fwrite(ucode_file,"\n\n************ Theia UCODE DUMP *******\n\n\n\n");
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$display("Opening Register lof file...\n");
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reg_log = $fopen("Registers.log","w");
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end
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`endif //Ucode dump
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//-----------------------------------------------------------------------
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`ifdef DEBUG
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wire [`WIDTH-1:0] wALUChannelX1,wALUChannelY1,wALUChannelZ1;
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wire [`WIDTH-1:0] wALUChannelX2,wALUChannelY2,wALUChannelZ2;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX1
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(
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.Clock( Clock ),
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.Reset( Reset),
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.Enable( wLatchNow ),
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.D( iSource1[95:64] ),
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.Q(wALUChannelX1)
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY1
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(
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.Clock( Clock ),
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.Reset( Reset),
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.Enable( wLatchNow ),
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.D( iSource1[63:32] ),
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.Q(wALUChannelY1)
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ1
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(
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.Clock( Clock ),
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.Reset( Reset),
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.Enable( wLatchNow ),
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.D( iSource1[31:0] ),
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.Q(wALUChannelZ1)
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceX2
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(
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.Clock( Clock ),
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.Reset( Reset),
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.Enable( wLatchNow ),
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.D( iSource0[95:64] ),
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.Q(wALUChannelX2)
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceY2
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(
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.Clock( Clock ),
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.Reset( Reset),
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.Enable( wLatchNow ),
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.D( iSource0[63:32] ),
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.Q(wALUChannelY2)
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) SourceZ2
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(
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.Clock( Clock ),
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.Reset( Reset),
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.Enable( wLatchNow ),
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.D( iSource0[31:0] ),
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.Q(wALUChannelZ2)
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);
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always @ (posedge iDecodeDone && iDebug_CoreID == `DEBUG_CORE)
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begin
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`LOGME"[CORE %d] IP:%d", iDebug_CoreID,iDebug_CurrentIP);
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end
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always @ (negedge Clock && iDebug_CoreID == `DEBUG_CORE)
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begin
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if ( iALUOutputReady )
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begin
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if (iBranchTaken)
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`LOGME"<BT>");
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if (iBranchNotTaken )
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`LOGME"<BNT>");
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if (oRAMWriteEnable)
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`LOGME"<WE>");
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`LOGME "(%dns ",$time);
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case ( oALUOperation )
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`RETURN: `LOGME"RETURN");
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`ADD: `LOGME"ADD");
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`SUB: `LOGME"SUB");
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`DIV: `LOGME"DIV");
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`MUL: `LOGME"MUL");
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`MAG: `LOGME"MAG");
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`JGX: `LOGME"JGX");
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`JLX: `LOGME"JLX");
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`JGEX: `LOGME"JGEX");
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`JGEY: `LOGME"JGEY");
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`JGEZ: `LOGME"JGEZ");
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`JLEX: `LOGME"JLEX");
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`JLEY: `LOGME"JLEY");
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`JLEZ: `LOGME"JLEZ");
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`JMP: `LOGME"JMP");
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`ZERO: `LOGME"ZERO");
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`JNEX: `LOGME"JNEX");
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`JNEY: `LOGME"JNEY");
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`JNEZ: `LOGME"JNEZ");
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`JEQX: `LOGME"JEQX");
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`JEQY: `LOGME"JEQY");
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`JEQZ: `LOGME"JEQZ");
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`CROSS: `LOGME"CROSS");
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`DOT: `LOGME"DOT");
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`SETX: `LOGME"SETX");
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`SETY: `LOGME"SETY");
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`SETZ: `LOGME"SETZ");
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`NOP: `LOGME"NOP");
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`COPY: `LOGME"COPY");
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`INC: `LOGME"INC");
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`DEC: `LOGME"DEC");
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`MOD: `LOGME"MOD");
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`FRAC: `LOGME"FRAC");
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`NEG: `LOGME"NEG");
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`SWIZZLE3D: `LOGME"SWIZZLE3D");
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`MULP: `LOGME"MULP");
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`XCHANGEX: `LOGME"XCHANGEX");
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`IMUL: `LOGME"IMUL");
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`UNSCALE: `LOGME"UNSCALE");
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`INCX: `LOGME"INCX");
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`INCY: `LOGME"INCY");
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`INCZ: `LOGME"INCZ");
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`OMWRITE: `LOGME"OMWRITE");
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`TMREAD: `LOGME"TMREAD");
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`LEA: `LOGME"LEA");
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`CALL: `LOGME"CALL");
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`RET: `LOGME"RET");
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`DEBUG_PRINT:
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begin
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`LOGME"DEBUG_PRINT");
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end
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default:
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begin
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`LOGME"**********ERROR UNKNOWN OP*********");
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$display("%dns EXE: Error Unknown Instruction : %d", $time,oALUOperation);
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// $stop();
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|
end
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|
endcase
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`LOGME"\t %h [ %h %h %h ][ %h %h %h ] = ",
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oRAMWriteAddress,
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|
wALUChannelX1,wALUChannelY1,wALUChannelZ1,
|
|
wALUChannelX2,wALUChannelY2,wALUChannelZ2
|
|
|
|
);
|
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|
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if (oALUOperation == `RETURN)
|
|
`LOGME"\n\n\n");
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|
end
|
|
end //always
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|
|
always @ ( negedge Clock && iDebug_CoreID == `DEBUG_CORE )
|
|
begin
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if ( iALUOutputReady )
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`LOGME" [ %h %h %h ])\n",iALUResultX,iALUResultY,iALUResultZ);
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end //always
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`endif
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endmodule
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