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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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//Square Root State Machine Constants
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`define SQUARE_ROOT_LOOP 1
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`define WRITE_SQUARE_ROOT_RESULT 2
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`define SR_AFTER_RESET_STATE 0
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//-----------------------------------------------------------------
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/*
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Calcualtes the SquareRoot of a Fixed Point Number
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Input: Q32.32
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Output: Q16.16
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Notice that the result has half the precicion as the operands!!
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*/
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module FixedPointSquareRoot
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(
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input wire Clock,
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input wire Reset,
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input wire[`LONG_WIDTH-1:0] Operand,
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input wire iInputReady,
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output reg OutputReady,
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output reg [`WIDTH-1:0] Result
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);
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reg[63:0] x;
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reg[0:`WIDTH-1] group,sum,diff;
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reg[0:`WIDTH-1] temp1,temp2;
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reg [5:0] CurrentState, NextState;
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reg myInputReady;
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//----------------------------------------
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always @(posedge Clock)
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begin
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myInputReady = iInputReady;
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end
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//----------------------------------------
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//Next states logic
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always @(negedge Clock)
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begin
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if( Reset!=1 )
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CurrentState = NextState;
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else
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CurrentState = `SR_AFTER_RESET_STATE;
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end
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//----------------------------------------
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always @ (posedge Clock)
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begin
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case (CurrentState)
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//----------------------------------------
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`SR_AFTER_RESET_STATE:
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begin
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OutputReady = 0;
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Result = 0;
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sum = 0;
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diff = 0;
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group=32; //WAS 16
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x = 0;
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if ( myInputReady == 1 )
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begin
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// x[31:0] = Operand;
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x = Operand;
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x = x << `SCALE;
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NextState = `SQUARE_ROOT_LOOP;
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end else
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NextState = `SR_AFTER_RESET_STATE;
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end
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//----------------------------------------
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`SQUARE_ROOT_LOOP:
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begin
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sum = sum << 1;
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sum = sum + 1;
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temp1 = diff << 2;
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//diff = diff + (x>>(group*2)) &3;
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temp2 = group << 1; //group * 2 ??
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diff = temp1 + ((x >> temp2) &3);
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if (sum > diff)
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begin
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sum = sum -1;
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end
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else
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begin
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Result = Result + (1<<group);
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diff = diff - sum;
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sum = sum + 1;
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end//if
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if ( group != 0 )
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begin
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group = group - 1;
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NextState = `SQUARE_ROOT_LOOP;
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end
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else
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begin
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NextState = `WRITE_SQUARE_ROOT_RESULT;
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end
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end
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//----------------------------------------
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`WRITE_SQUARE_ROOT_RESULT:
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begin
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OutputReady = 1;
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NextState = (iInputReady == 0) ?
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`SR_AFTER_RESET_STATE : `WRITE_SQUARE_ROOT_RESULT;
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end
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//----------------------------------------
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endcase
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end //always
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endmodule
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//-----------------------------------------------------------------
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