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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 19:49:14 01/13/2009
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// Design Name:
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// Module Name: RadixRMul
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`default_nettype none
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//---------------------------------------------------
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module MUX_4_TO_1_32Bits_FullParallel
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(
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input wire [31:0] i1,i2,i3,i4,
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output reg [31:0] O,
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input wire [1:0] Sel
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);
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always @ ( Sel or i1 or i2 or i3 or i4 )
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begin
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case (Sel)
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2'b00: O = i1;
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2'b01: O = i2;
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2'b10: O = i3;
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2'b11: O = i4;
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endcase
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end
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endmodule
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//---------------------------------------------------
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/*
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module SHIFTER2_16_BITS
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(
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input wire C,
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input wire[15:0] In,
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output reg[15:0] Out
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);
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reg [15:0] Temp;
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always @ (posedge C )
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begin
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Out = In << 2;
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end
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endmodule
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*/
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//---------------------------------------------------
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module RADIX_R_MUL_32_FULL_PARALLEL
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(
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input wire Clock,
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input wire Reset,
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input wire[31:0] A,
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input wire[31:0] B,
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output wire[63:0] R,
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input wire iUnscaled,
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input wire iInputReady,
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output wire OutputReady
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);
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wire wInputDelay1;
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//-------------------
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wire [31:0] wALatched,wBLatched;
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) FFD1
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(
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.Clock( Clock ),
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.Reset( Reset),
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.Enable( iInputReady ),
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.D( A ),
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.Q( wALatched)
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `WIDTH ) FFD2
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(
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.Clock( Clock ),
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.Reset( Reset),
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.Enable( iInputReady ),
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.D( B ),
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.Q( wBLatched )
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);
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//-------------------
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FFD_POSEDGE_ASYNC_RESET #(1) FFOutputReadyDelay1
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(
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.Clock( Clock ),
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.Clear( Reset ),
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.D( iInputReady ),
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.Q( wInputDelay1 )
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);
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FFD_POSEDGE_ASYNC_RESET #(1) FFOutputReadyDelay2
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(
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.Clock( Clock ),
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.Clear( Reset ),
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.D( wInputDelay1 ),
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.Q( OutputReady )
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);
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wire [31:0] wA, w2A, w3A, wB;
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wire SignA,SignB;
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assign SignA = wALatched[31];
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assign SignB = wBLatched[31];
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assign wB = (SignB == 1) ? ~wBLatched + 1'b1 : wBLatched;
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assign wA = (SignA == 1) ? ~wALatched + 1'b1 : wALatched;
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assign w2A = wA << 1;
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assign w3A = w2A + wA;
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wire [31:0] wPartialResult0,wPartialResult1,wPartialResult2,wPartialResult3,wPartialResult4,wPartialResult5;
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wire [31:0] wPartialResult6,wPartialResult7,wPartialResult8,wPartialResult9,wPartialResult10,wPartialResult11;
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wire [31:0] wPartialResult12,wPartialResult13,wPartialResult14,wPartialResult15;
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MUX_4_TO_1_32Bits_FullParallel MUX0
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[1],wB[0]} ),
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.O( wPartialResult0 )
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);
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MUX_4_TO_1_32Bits_FullParallel MUX1
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[3],wB[2]} ),
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.O( wPartialResult1 )
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);
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MUX_4_TO_1_32Bits_FullParallel MUX2
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[5],wB[4]} ),
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.O( wPartialResult2 )
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);
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MUX_4_TO_1_32Bits_FullParallel MUX3
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[7],wB[6]} ),
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.O( wPartialResult3 )
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);
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MUX_4_TO_1_32Bits_FullParallel MUX4
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[9],wB[8]} ),
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.O( wPartialResult4 )
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);
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MUX_4_TO_1_32Bits_FullParallel MUX5
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[11],wB[10]} ),
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.O( wPartialResult5 )
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);
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MUX_4_TO_1_32Bits_FullParallel MUX6
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[13],wB[12]} ),
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.O( wPartialResult6 )
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);
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MUX_4_TO_1_32Bits_FullParallel MUX7
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[15],wB[14]} ),
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.O( wPartialResult7 )
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);
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MUX_4_TO_1_32Bits_FullParallel MUX8
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[17],wB[16]} ),
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.O( wPartialResult8 )
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);
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MUX_4_TO_1_32Bits_FullParallel MUX9
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[19],wB[18]} ),
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.O( wPartialResult9 )
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);
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MUX_4_TO_1_32Bits_FullParallel MUX10
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[21],wB[20]} ),
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.O( wPartialResult10 )
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);
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MUX_4_TO_1_32Bits_FullParallel MUX11
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[23],wB[22]} ),
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.O( wPartialResult11 )
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);
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MUX_4_TO_1_32Bits_FullParallel MUX12
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[25],wB[24]} ),
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.O( wPartialResult12 )
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);
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MUX_4_TO_1_32Bits_FullParallel MUX13
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[27],wB[26]} ),
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.O( wPartialResult13 )
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);
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MUX_4_TO_1_32Bits_FullParallel MUX14
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[29],wB[28]} ),
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.O( wPartialResult14 )
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);
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MUX_4_TO_1_32Bits_FullParallel MUX15
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(
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.i1( 32'b 0 ),
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.i2( wA ),
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.i3( w2A ),
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.i4( w3A ),
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.Sel( {wB[31],wB[30]} ),
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.O( wPartialResult15 )
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);
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wire[63:0] wPartialResult1_0,wPartialResult1_1,wPartialResult1_2,wPartialResult1_3,
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wPartialResult1_4,wPartialResult1_5,wPartialResult1_6,wPartialResult1_7;
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assign wPartialResult1_0 = (wPartialResult0) + (wPartialResult1<<2);
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assign wPartialResult1_1 = (wPartialResult2 << 4) + (wPartialResult3<<6);
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assign wPartialResult1_2 = (wPartialResult4 << 8) + (wPartialResult5<<10);
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assign wPartialResult1_3 = (wPartialResult6 << 12)+ (wPartialResult7<<14);
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assign wPartialResult1_4 = (wPartialResult8 << 16)+ (wPartialResult9<<18);
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assign wPartialResult1_5 = (wPartialResult10 << 20) + (wPartialResult11<< 22);
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assign wPartialResult1_6 = (wPartialResult12 << 24) + (wPartialResult13 << 26);
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assign wPartialResult1_7 = (wPartialResult14 << 28) + (wPartialResult15 << 30);
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wire [63:0] wPartialResult2_0,wPartialResult2_1,wPartialResult2_2,wPartialResult2_3;
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assign wPartialResult2_0 = wPartialResult1_0 + wPartialResult1_1;
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assign wPartialResult2_1 = wPartialResult1_2 + wPartialResult1_3;
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assign wPartialResult2_2 = wPartialResult1_4 + wPartialResult1_5;
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assign wPartialResult2_3 = wPartialResult1_6 + wPartialResult1_7;
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wire [63:0] wPartialResult3_0,wPartialResult3_1;
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assign wPartialResult3_0 = wPartialResult2_0 + wPartialResult2_1;
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assign wPartialResult3_1 = wPartialResult2_2 + wPartialResult2_3;
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wire [63:0] R_pre1,R_pre2;
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//assign R_pre1 = (wPartialResult3_0 + wPartialResult3_1);
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assign R_pre1 = (iUnscaled == 1) ? (wPartialResult3_0 + wPartialResult3_1) : ((wPartialResult3_0 + wPartialResult3_1) >> `SCALE);
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assign R_pre2 = ( (SignA ^ SignB) == 1) ? ~R_pre1 + 1'b1 : R_pre1;
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//assign R = R_pre2 >> `SCALE;
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assign R = R_pre2;
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endmodule
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No newline at end of file
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No newline at end of file
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