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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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/**********************************************************************************
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Theia, Ray Cast Programable graphic Processing Unit.
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Copyright (C) 2010 Diego Valverde (diego.valverde.g@gmail.com)
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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***********************************************************************************/
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//---------------------------------------------------------------------------
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module THEIA
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(
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input wire CLK_I, //Input clock
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input wire RST_I, //Input reset
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//Theia Interfaces
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input wire MST_I, //Master signal, THEIA enters configuration mode
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//when this gets asserted (see documentation)
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//Wish Bone Interface
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input wire [`WB_WIDTH-1:0] DAT_I, //Input data bus (Wishbone)
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input wire ACK_I, //Input ack
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output wire ACK_O, //Output ack
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input wire [`WB_WIDTH-1:0] ADR_I, //Input address
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input wire WE_I, //Input write enable
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input wire STB_I, //Strobe signal, see wishbone documentation
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input wire CYC_I, //Bus cycle signal, see wishbone documentation
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input wire [1:0] TGA_I, //Input address tag, see THEAI documentation
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input wire [`MAX_CORES-1:0] SEL_I, //The WishBone Master uses this signal to configure a specific core (TBD, not sure is needed)
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input wire [`MAX_CORES-1:0] RENDREN_I,
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input wire [`MAX_CORE_BITS-1:0] OMBSEL_I, //Output memory bank select
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input wire [`WB_WIDTH-1:0] OMADR_I, //Output adress (relative to current bank)
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output wire [`WB_WIDTH-1:0] OMEM_O, //Output data bus (Wishbone)
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input wire [`WB_WIDTH-1:0] TMDAT_I,
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input wire [`WB_WIDTH-1:0] TMADR_I,
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input wire TMWE_I,
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input wire [`MAX_TMEM_BANKS-1:0] TMSEL_I,
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//Control Register
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input wire [15:0] CREG_I,
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output wire HDL_O,
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input wire STDONE_I,
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input wire HDA_I,
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input wire HDLACK_I,
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output wire RCOMMIT_O,
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output wire DONE_O
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);
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wire [`MAX_TMEM_BANKS-1:0] wTMemWriteEnable;
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SELECT_1_TO_N # ( `MAX_TMEM_BANKS, `MAX_TMEM_BANKS ) TMWE_SEL
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(
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.Sel(TMSEL_I),
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.En(TMWE_I),
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.O(wTMemWriteEnable)
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);
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wire [`MAX_CORES-1:0] wDone;
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wire [`MAX_CORES-1:0] wBusGranted,wBusRequest;
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//wire [`WB_WIDTH-1:0] wDAT_O[`MAX_CORES-1:0];
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//wire [`WB_WIDTH-1:0] wADR_O[`MAX_CORES-1:0];
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//wire [1:0] wTGA_O[`MAX_CORES-1:0];
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wire [`MAX_CORE_BITS-1:0] wBusSelect;
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//wire [`MAX_CORES-1:0] wSTB_O;
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//wire [`MAX_CORES-1:0] wWE_O;
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wire [`MAX_CORES-1:0]wACK_O;
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wire wOMem_WE[`MAX_CORES-1:0];
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wire [`WB_WIDTH-1:0] wOMEM_Address[`MAX_CORES-1:0];
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wire [`WB_WIDTH-1:0] wOMEM_Dat[`MAX_CORES-1:0];
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wire [`MAX_CORES-1:0] wSTB_I;
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wire [`MAX_CORES-1:0] wMST_I;
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wire [`MAX_CORES-1:0] wACK_I;
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wire [`MAX_CORES-1:0] wCYC_I;
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wire [1:0] wTGA_I[`MAX_CORES-1:0];
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wire [`WB_WIDTH-1:0] wTMEM_Data;
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wire [`WB_WIDTH-1:0] wTMEM_Address[`MAX_CORES-1:0];
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wire [`WB_WIDTH-1:0] wTMEM_ReadAddr;
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wire [`MAX_CORES-1:0] wTMEM_Resquest;
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wire [`MAX_CORES-1:0] wTMEM_Granted;
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//CROSS-BAR cables
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wire [`WB_WIDTH-1:0] wCrossBarDataRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank
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wire [`WB_WIDTH-1:0] wCrossBarDataCollumn[`MAX_CORES-1:0]; //Vertical grid buses comming from each core.
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wire [`WB_WIDTH-1:0] wTMemReadAdr[`MAX_CORES-1:0]; //Horizontal grid Buses comming from each core (virtual addr).
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wire [`WB_WIDTH-1:0] wCrossBarAdressCollumn[`MAX_CORES-1:0]; //Vertical grid buses comming from each core. (physical addr).
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wire [`WB_WIDTH-1:0] wCrossBarAddressRow[`MAX_TMEM_BANKS-1:0]; //Horizontal grid Buses comming from each bank.
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wire wCORE_2_TMEM__Req[`MAX_CORES-1:0];
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wire [`MAX_TMEM_BANKS -1:0] wBankReadRequest[`MAX_CORES-1:0];
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wire [`MAX_CORES-1:0] wBankReadGranted[`MAX_TMEM_BANKS-1:0];
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wire wTMEM_2_Core__Grant[`MAX_CORES-1:0];
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wire[`MAX_CORE_BITS-1:0] wCurrentCoreSelected[`MAX_TMEM_BANKS-1:0];
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wire[`WIDTH-1:0] wCoreBankSelect[`MAX_CORES-1:0];
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wire [`MAX_CORES-1:0] wHDL_O;
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wire [`MAX_CORES-1:0] wHostDataLatched;
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wire [`MAX_CORES-1:0] wRCOMMIT_O;
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wire [`MAX_CORES-1:0] wRCommited;
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assign RCOMMIT_O = wRCommited[0] & wRCommited[1] & wRCommited[2] & wRCommited[3];
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assign HDL_O = wHostDataLatched[0] & wHostDataLatched[1] & wHostDataLatched[2] & wHostDataLatched[3];
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assign DONE_O = wDone[0] & wDone[1] & wDone[2] & wDone[3];
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//----------------------------------------------------------------
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Module_BusArbitrer ARB1
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(
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.Clock( CLK_I ),
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.Reset( RST_I ),
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.iRequest( wBusRequest ),
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.oGrant( wBusGranted ),
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.oBusSelect( wBusSelect )
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);
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//----------------------------------------------------------------
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wire wMaskedACK_O;
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assign wMaskedACK_O = (SEL_I & wACK_O) ? 1'b1 : 1'b0;
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assign ACK_O = ( MST_I ) ? wMaskedACK_O : wACK_O[ wBusSelect];
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wire [`WB_WIDTH-1:0] wDataOut[`MAX_CORES-1:0];
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assign OMEM_O = wDataOut[ OMBSEL_I ];
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genvar i;
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generate
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for (i = 0; i < `MAX_CORES; i = i +1)
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begin : CORE
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assign wMST_I[i] = (SEL_I[i]) ? MST_I : 0;
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assign wSTB_I[i] = (SEL_I[i]) ? STB_I : 0;
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assign wCYC_I[i] = (SEL_I[i]) ? CYC_I : 0;
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assign wTGA_I[i] = (SEL_I[i]) ? TGA_I : 0;
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THEIACORE CTHEIA
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(
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.CLK_I( CLK_I ),
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.RST_I( RST_I ),
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.RENDREN_I( RENDREN_I[i] ),
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//Slave signals
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.ADR_I( ADR_I ),
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.WE_I( WE_I ),
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.STB_I( wSTB_I[i] ),
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.ACK_I( ACK_I ),
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.CYC_I( wCYC_I[i] ),
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.MST_I( wMST_I[i] ),
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.TGA_I( wTGA_I[i] ),
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.CREG_I( CREG_I ),
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//Master Signals
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.ACK_O( wACK_O[i] ),
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.CYC_O( wBusRequest[i] ),
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.GNT_I( wBusGranted[i] ),
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`ifdef DEBUG
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.iDebug_CoreID( i ),
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`endif
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.OMEM_WE_O( wOMem_WE[i] ),
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.OMEM_ADR_O( wOMEM_Address[i] ),
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.OMEM_DAT_O( wOMEM_Dat[i] ),
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.TMEM_DAT_I( wCrossBarDataCollumn[i] ),
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.TMEM_ADR_O( wTMemReadAdr[i] ),
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.TMEM_CYC_O( wCORE_2_TMEM__Req[i] ),
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.TMEM_GNT_I( wTMEM_2_Core__Grant[i] ),
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.HDA_I( HDA_I ), //Host data available
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.HDL_O( wHDL_O[i] ), //Host data Latched
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.HDLACK_I( ~HDL_O ), //Host data Latched ACK
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.STDONE_I( STDONE_I ),
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.RCOMMIT_O( wRCOMMIT_O[i] ),
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//Other
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.DAT_I( DAT_I ),
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.DONE_O( wDone[i] )
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);
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UPCOUNTER_POSEDGE # (1) UP_RCOMMIT
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(
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.Clock( CLK_I ),
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.Reset( RST_I | HDLACK_I ),
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.Initial( 1'b0 ),
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.Enable( wRCOMMIT_O[i] ),
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.Q(wRCommited[i])
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);
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UPCOUNTER_POSEDGE # (1) UP_GREADY
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(
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.Clock( CLK_I ),
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.Reset( RST_I | HDLACK_I ),
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.Initial( 1'b0 ),
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.Enable( wHDL_O[i] ),
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.Q(wHostDataLatched[i])
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);
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RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 250000 ) OMEM //500000 ) OMEM
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(
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.Clock( CLK_I ),
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.iWriteEnable( wOMem_WE[i] ),
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.iWriteAddress( wOMEM_Address[i] ),
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.iDataIn( wOMEM_Dat[i] ),
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.iReadAddress0( OMADR_I ),
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.oDataOut0( wDataOut[i] )
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);
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//If there are "n" banks, memory location "X" would reside in bank number X mod n.
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//X mod 2^n == X & (2^n - 1)
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assign wCoreBankSelect[i] = (wTMemReadAdr[i] & (`MAX_TMEM_BANKS-1));
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//Each core has 1 bank request slot
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//Each slot has MAX_TMEM_BANKS bits. Only 1 bit can
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//be 1 at any given point in time. All bits zero means,
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//we are not requesting to read from any memory bank.
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SELECT_1_TO_N # ( `WIDTH, `MAX_CORES ) READDRQ
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(
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.Sel(wCoreBankSelect[ i]),
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.En(wCORE_2_TMEM__Req[i]),
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.O(wBankReadRequest[i])
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);
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//The address coming from the core is virtual adress, meaning it assumes linear
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//address space, however, since memory is interleaved in a n-way memory we transform
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//virtual adress into physical adress (relative to the bank) like this
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//fadr = vadr / n = vadr >> log2(n)
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assign wCrossBarAdressCollumn[i] = (wTMemReadAdr[i] >> `MAX_CORE_BITS);
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//Connect the granted signal to Arbiter of the Bank we want to read from
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assign wTMEM_2_Core__Grant[i] = wBankReadGranted[wCoreBankSelect[i]][i];
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//Connect the request signal to Arbiter of the Bank we want to read from
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//assign wBankReadRequest[wCoreBankSelect[i]][i] = wCORE_2_TMEM__Req[i];
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end
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endgenerate
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////////////// CROSS-BAR INTERCONECTION//////////////////////////
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genvar Core,Bank;
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generate
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for (Bank = 0; Bank < `MAX_TMEM_BANKS; Bank = Bank + 1)
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begin : BANK
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//The memory bank itself
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RAM_SINGLE_READ_PORT # ( `WB_WIDTH, `WB_WIDTH, 50000 ) TMEM
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(
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.Clock( CLK_I ),
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.iWriteEnable( wTMemWriteEnable[Bank] ),
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.iWriteAddress( TMADR_I ),
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.iDataIn( TMDAT_I ),
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.iReadAddress0( wCrossBarAddressRow[Bank] ), //Connect to the Row of the grid
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.oDataOut0( wCrossBarDataRow[Bank] ) //Connect to the Row of the grid
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);
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//Arbiter will Round-Robin Cores attempting to read from the same Bank
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//at a given point in time
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wire [`MAX_CORES-1:0] wBankReadGrantedDelay[`MAX_TMEM_BANKS-1:0];
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Module_BusArbitrer ARB_TMEM
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(
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.Clock( CLK_I ),
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.Reset( RST_I ),
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.iRequest( {wBankReadRequest[3][Bank],wBankReadRequest[2][Bank],wBankReadRequest[1][Bank],wBankReadRequest[0][Bank]}),
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.oGrant( wBankReadGrantedDelay[Bank] ), //The bit of the core granted to read from this Bank
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.oBusSelect( wCurrentCoreSelected[Bank] ) //The index of the core granted to read from this Bank
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);
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FFD_POSEDGE_SYNCRONOUS_RESET # ( `MAX_CORES ) FFD_GNT
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(
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.Clock(CLK_I),
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.Reset(RST_I),
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.Enable( 1'b1 ),
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.D(wBankReadGrantedDelay[Bank]),
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.Q(wBankReadGranted[Bank])
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);
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//Create the Cross-Bar interconnection grid now, rows are coonected to the memory banks,
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//while collumns are connected to the cores, 2 or more cores can not read from the same
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//bank at any given point in time
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for (Core = 0; Core < `MAX_CORES; Core = Core + 1)
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begin: CORE_CONNECT
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//Connect the Data Collum of this core to the Data Row of current bank, only if the Core is looking for data stored in this bank
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assign wCrossBarDataCollumn[ Core ] = ( wCoreBankSelect[ Core ] == Bank ) ? wCrossBarDataRow[ Bank ] : `WB_WIDTH'bz;
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//Connect the Address Row of this Bank to the Address Column of the core, only if the Arbiter selected this core for reading
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assign wCrossBarAddressRow[ Bank ] = ( wCurrentCoreSelected[ Bank ] == Core ) ? wCrossBarAdressCollumn[Core]: `WB_WIDTH'bz;
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end
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end
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endgenerate
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////////////// CROSS-BAR INTERCONECTION//////////////////////////
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//----------------------------------------------------------------
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endmodule
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//---------------------------------------------------------------------------
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No newline at end of file
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No newline at end of file
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