| Line 28... |
Line 28... |
It also implements a second processs that simulates a Wishbone slave that sends
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It also implements a second processs that simulates a Wishbone slave that sends
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data from an external memory. These blocks are just behavioral CTE and therefore
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data from an external memory. These blocks are just behavioral CTE and therefore
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are not meant to be synthethized.
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are not meant to be synthethized.
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*******************************************************************************/
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*******************************************************************************/
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "aDefinitions.v"
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`include "aDefinitions.v"
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`define CONFIGURATION_PHASE 0
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`define CONFIGURATION_PHASE 0
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`define CTE_INITIAL_STATE 0
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`define CTE_INITIAL_STATE 0
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`define CTE_IDLE 1
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`define CTE_IDLE 1
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| Line 108... |
Line 110... |
integer file, log, r, a, b;
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integer file, log, r, a, b;
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reg [31:0] rSceneParameters[31:0];
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reg [31:0] rSceneParameters[31:0];
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reg [31:0] rVertexBuffer[6000:0];
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reg [31:0] rVertexBuffer[6000:0];
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reg [31:0] rInstructionBuffer[25:0];
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reg [31:0] rInstructionBuffer[512:0];
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`define TEXTURE_BUFFER_SIZE (256*256*3)
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`define TEXTURE_BUFFER_SIZE (256*256*3)
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reg [31:0] rTextures[`TEXTURE_BUFFER_SIZE:0]; //Lets asume we use 256*256 textures
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reg [31:0] rTextures[`TEXTURE_BUFFER_SIZE:0]; //Lets asume we use 256*256 textures
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//------------------------------------------------------------------------
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//------------------------------------------------------------------------
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//Debug registers
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//Debug registers
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| Line 166... |
Line 168... |
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//---------------------------------------------
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//---------------------------------------------
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//generate the clock signal here
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//generate the clock signal here
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always begin
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always begin
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#5 Clock = ! Clock;
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#`CLOCK_CYCLE Clock = ! Clock;
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end
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end
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//---------------------------------------------
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//---------------------------------------------
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reg [15:0] rTimeOut;
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reg [15:0] rTimeOut;
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| Line 400... |
Line 402... |
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end
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end
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ACK_O = 1;
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ACK_O = 1;
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//if (ADR_I >= `RESOLUTION_WIDTH*`RESOLUTION_HEIGHT*3)
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if (CurrentPixelCol >= `RESOLUTION_HEIGHT)
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if (CurrentPixelCol >= `RESOLUTION_HEIGHT)
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WBSNextState = `WBS_DONE;
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WBSNextState = `WBS_DONE;
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else
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else
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WBSNextState = `WBS_MOINTOR_STB_I_NEG;
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WBSNextState = `WBS_MOINTOR_STB_I_NEG;
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end
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end
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| Line 435... |
Line 437... |
$fclose(ucode_file);
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$fclose(ucode_file);
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end
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end
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//----------------------------------------
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//----------------------------------------
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default:
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default:
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begin
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begin
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$display("WTF????????????????????????");
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$display("WBS Undefined state");
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end
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end
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endcase
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endcase
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end //end always
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end //end always
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//----------------------------------------------------------
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//----------------------------------------------------------
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| Line 520... |
Line 522... |
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assign DAT_O = ( MST_O == 1'b1 ) ? wMasteData_O : rSlaveData_O;
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assign DAT_O = ( MST_O == 1'b1 ) ? wMasteData_O : rSlaveData_O;
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wire[31:0] wMasteData_O;
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wire[31:0] wMasteData_O;
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assign wMasteData_O = (TGA_O == `TAG_INSTRUCTION_ADDRESS_TYPE) ? rInstructionBuffer[rInstructionPointer] : rSceneParameters[ rDataPointer ];
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assign wMasteData_O = (TGA_O == `TAG_INSTRUCTION_ADDRESS_TYPE) ? rInstructionBuffer[rInstructionPointer+1] : rSceneParameters[ rDataPointer ];
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always @ (posedge STB_O)
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begin
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if (TGA_O == `TAG_INSTRUCTION_ADDRESS_TYPE)
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begin
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$display("-- %x\n",wMasteData_O);
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end
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end
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assign ADR_O = rAddressToSend;
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assign ADR_O = rAddressToSend;
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reg [7:0] WBMCurrentState,WBMNextState;
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reg [7:0] WBMCurrentState,WBMNextState;
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reg [31:0] rWriteAddress;
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reg [31:0] rWriteAddress;
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| Line 545... |
Line 558... |
//----------------------------------------------------------
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//----------------------------------------------------------
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always @(posedge Clock)
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always @(posedge Clock)
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begin
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begin
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case (WBMCurrentState)
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case (WBMCurrentState)
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//----------------------------------------
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//----------------------------------------
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/*
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Wait until the reset secuence is complete to
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//Wait until the reset secuence is complete to
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begin sending stuff.
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//begin sending stuff.
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*/
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`WBM_AFTER_RESET:
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`WBM_AFTER_RESET:
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begin
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begin
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WE_O <= 0;
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WE_O <= 0;
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CYC_O <= 0;
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CYC_O <= 0;
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TGC_O <= 0;
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TGC_O <= 0;
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| Line 569... |
Line 582... |
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
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WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
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else
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else
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WBMNextState <= `WBM_AFTER_RESET;
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WBMNextState <= `WBM_AFTER_RESET;
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end
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end
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//----------------------------------------
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//----------------------------------------
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/*
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CLOCK EDGE 0: MASTER presents a valid address on [ADR_O()]
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//CLOCK EDGE 0: MASTER presents a valid address on [ADR_O()]
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MASTER presents valid data on [DAT_O()]
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//MASTER presents valid data on [DAT_O()]
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MASTER asserts [WE_O] to indicate a WRITE cycle.
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//MASTER asserts [WE_O] to indicate a WRITE cycle.
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MASTER asserts [CYC_O] and [TGC_O()] to indicate the start of the cycle.
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//MASTER asserts [CYC_O] and [TGC_O()] to indicate the start of the cycle.
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MASTER asserts [STB_O] to indicate the start of the phase.
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//MASTER asserts [STB_O] to indicate the start of the phase.
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*/
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`WBM_WRITE_INSTRUCTION_PHASE1:
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`WBM_WRITE_INSTRUCTION_PHASE1:
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begin
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begin
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WE_O <= 1; //Indicate write cycle
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WE_O <= 1; //Indicate write cycle
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CYC_O <= 1; //Start of the cycle
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CYC_O <= 1; //Start of the cycle
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TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
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TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
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| Line 655... |
Line 668... |
IncDP <= 0;
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IncDP <= 0;
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rResetDp <= 1;
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rResetDp <= 1;
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if (rInstructionPointer >= 4)
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if (rInstructionPointer >= rInstructionBuffer[0])
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begin
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begin
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IncIA <= 0;//*
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IncIA <= 0;//*
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rClearOutAddress <= 1;
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rClearOutAddress <= 1;
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WBMNextState <= `WBM_SEND_DATA_PHASE1;
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WBMNextState <= `WBM_SEND_DATA_PHASE1;
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end
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end
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| Line 816... |
Line 829... |
WBMNextState <= `WBM_SEND_DATA_PHASE1;
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WBMNextState <= `WBM_SEND_DATA_PHASE1;
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end
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end
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//----------------------------------------
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//----------------------------------------
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/*
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Here everything is ready so just start!
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//Here everything is ready so just start!
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*/
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`WBM_DONE:
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`WBM_DONE:
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begin
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begin
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WE_O <= 0;
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WE_O <= 0;
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CYC_O <= 0;
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CYC_O <= 0;
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TGC_O <= 0;
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TGC_O <= 0;
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