| Line 61... |
Line 61... |
`define RESOLUTION_HEIGHT (rSceneParameters[13] >> `SCALE)
|
`define RESOLUTION_HEIGHT (rSceneParameters[13] >> `SCALE)
|
`define RAYI_TASK 1
|
`define RAYI_TASK 1
|
`define DELTA_ROW (32'h1 << `SCALE)
|
`define DELTA_ROW (32'h1 << `SCALE)
|
`define DELTA_COL (32'h1 << `SCALE)
|
`define DELTA_COL (32'h1 << `SCALE)
|
|
|
|
`define SELECT_ALL_CORES `MAX_CORES'b0011;
|
module TestBench_Theia;
|
module TestBench_Theia;
|
|
|
|
|
//------------------------------------------------------------------------
|
//------------------------------------------------------------------------
|
//**WARNING: Declare all of your varaibles at the begining
|
//**WARNING: Declare all of your varaibles at the begining
|
| Line 92... |
Line 93... |
wire [`WB_WIDTH-1:0] DAT_O;
|
wire [`WB_WIDTH-1:0] DAT_O;
|
|
|
reg ACK_O;
|
reg ACK_O;
|
wire ACK_I;
|
wire ACK_I;
|
wire [`WB_WIDTH-1:0] ADR_I,ADR_O;
|
wire [`WB_WIDTH-1:0] ADR_I,ADR_O;
|
wire WE_I,STB_I,CYC_I;
|
wire WE_I,STB_I;
|
reg CYC_O,WE_O,TGC_O,STB_O;
|
reg CYC_O,WE_O,TGC_O,STB_O;
|
wire [1:0] TGC_I;
|
wire [1:0] TGC_I;
|
reg [1:0] TGA_O;
|
reg [1:0] TGA_O;
|
wire [1:0] TGA_I;
|
wire [1:0] TGA_I;
|
wire [31:0] DAT_I;
|
wire [31:0] DAT_I;
|
| Line 114... |
Line 115... |
reg [31:0] rVertexBuffer[6000:0];
|
reg [31:0] rVertexBuffer[6000:0];
|
reg [31:0] rInstructionBuffer[512:0];
|
reg [31:0] rInstructionBuffer[512:0];
|
`define TEXTURE_BUFFER_SIZE (256*256*3)
|
`define TEXTURE_BUFFER_SIZE (256*256*3)
|
reg [31:0] rTextures[`TEXTURE_BUFFER_SIZE:0]; //Lets asume we use 256*256 textures
|
reg [31:0] rTextures[`TEXTURE_BUFFER_SIZE:0]; //Lets asume we use 256*256 textures
|
|
|
|
integer i,j;
|
|
`define MAX_WIDTH 200
|
|
`define MAX_SCREENBUFFER (`MAX_WIDTH*`MAX_WIDTH*3)
|
|
reg [7:0] rScreen[`MAX_SCREENBUFFER-1:0];
|
|
|
//------------------------------------------------------------------------
|
//------------------------------------------------------------------------
|
//Debug registers
|
//Debug registers
|
`define TASK_TIMEOUTMAX 150000//50000
|
`define TASK_TIMEOUTMAX 150000//50000
|
|
|
|
|
| Line 126... |
Line 132... |
|
|
|
|
|
|
reg MST_O;
|
reg MST_O;
|
//---------------------------------------------------------------
|
//---------------------------------------------------------------
|
THEIACORE THEIA
|
|
|
wire [3:0] CYC_I,GNT_O;
|
|
wire wDone;
|
|
reg [`MAX_CORES-1:0] rCoreSelect,rRenderEnable;
|
|
|
|
THEIA GPU
|
(
|
(
|
.CLK_I( Clock ),
|
.CLK_I( Clock ),
|
.RST_I( Reset ),
|
.RST_I( Reset ),
|
|
.RENDREN_I( rRenderEnable ),
|
.DAT_I( DAT_O ),
|
.DAT_I( DAT_O ),
|
.ADR_O( ADR_I ),
|
.ADR_O( ADR_I ),
|
.ACK_I( ACK_O ),
|
.ACK_I( ACK_O ),
|
.WE_O ( WE_I ),
|
.WE_O ( WE_I ),
|
.STB_O( STB_I ),
|
.STB_O( STB_I ),
|
.CYC_O( CYC_I ),
|
|
.CYC_I( CYC_O ),
|
.CYC_I( CYC_O ),
|
.TGC_O( TGC_I ),
|
.TGC_O( TGC_I ),
|
.MST_I( MST_O ),
|
.MST_I( MST_O ),
|
.TGA_I( TGA_O ),
|
.TGA_I( TGA_O ),
|
.ACK_O( ACK_I ),
|
.ACK_O( ACK_I ),
|
.ADR_I( ADR_O ),
|
.ADR_I( ADR_O ),
|
.DAT_O( DAT_I ),
|
.DAT_O( DAT_I ),
|
.WE_I( WE_O ),
|
.WE_I( WE_O ),
|
|
.SEL_I( rCoreSelect ),//4'b0001 ),
|
.STB_I( STB_O ),
|
.STB_I( STB_O ),
|
.TGA_O(TGA_I),
|
.TGA_O(TGA_I),
|
|
|
|
|
|
|
|
|
//Control register
|
//Control register
|
.CREG_I( rControlRegister[0][15:0] )
|
.CREG_I( rControlRegister[0][15:0] ),
|
//Other stuff
|
//Other stuff
|
|
.DONE_O( wDone )
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
);
|
|
//&
|
|
//---------------------------------------------------------------
|
|
|
|
|
|
//---------------------------------------------
|
//---------------------------------------------
|
//generate the clock signal here
|
//generate the clock signal here
|
always begin
|
always begin
|
#`CLOCK_CYCLE Clock = ! Clock;
|
#`CLOCK_CYCLE Clock = ! Clock;
|
|
|
| Line 192... |
Line 197... |
rLaneD = 32'b0;
|
rLaneD = 32'b0;
|
ExternalBus_DataReady = 0;
|
ExternalBus_DataReady = 0;
|
rTimeOut = 0;
|
rTimeOut = 0;
|
|
|
|
|
|
|
`ifdef DUMP_CODE
|
`ifdef DUMP_CODE
|
$write("Opening TestBench.log.... ");
|
$write("Opening TestBench.log.... ");
|
ucode_file = $fopen("TestBench.log","w");
|
ucode_file = $fopen("TestBench.log","w");
|
$display("Done");
|
$display("Done");
|
`endif
|
`endif
|
| Line 327... |
Line 333... |
WBSNextState = `WBS_MOINTOR_STB_I;
|
WBSNextState = `WBS_MOINTOR_STB_I;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
`WBS_MOINTOR_STB_I:
|
`WBS_MOINTOR_STB_I:
|
begin
|
begin
|
if ( STB_I == 1 )
|
if ( STB_I == 1 && wDone == 0)
|
WBSNextState = `WBS_ACK_O;
|
WBSNextState = `WBS_ACK_O;
|
else
|
else if (STB_I == 0 && wDone == 0)
|
WBSNextState = `WBS_MOINTOR_STB_I;
|
WBSNextState = `WBS_MOINTOR_STB_I;
|
|
else
|
|
WBSNextState = `WBS_DONE;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
`WBS_ACK_O:
|
`WBS_ACK_O:
|
begin
|
begin
|
if (WE_I == 0)
|
if (WE_I == 0)
|
| Line 355... |
Line 363... |
`LOGME"WB SLAVE: MASTER Requested read from texture address: %h (%d)Data = %h \n",rAddress, rConvertedTextureAddress,DAT_O );
|
`LOGME"WB SLAVE: MASTER Requested read from texture address: %h (%d)Data = %h \n",rAddress, rConvertedTextureAddress,DAT_O );
|
`endif
|
`endif
|
end
|
end
|
else
|
else
|
begin
|
begin
|
Thingy = 0;
|
// Thingy = 0; //THIS IS NOT RE-ENTRANT!!!
|
rSlaveData_O = rVertexBuffer[ rAddress ];
|
rSlaveData_O = rVertexBuffer[ rAddress ];
|
`ifdef DEBUG
|
`ifdef DEBUG
|
`LOGME"WB SLAVE: MASTER Requested read from vertex address: %h Data = %h\n",rAddress,DAT_O);
|
`LOGME"WB SLAVE: MASTER Requested read from vertex address: %h Data = %h\n",rAddress,DAT_O);
|
`endif
|
`endif
|
end
|
end
|
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// $display("Theia Writes value: %h @ %h (Time to process pixel %d Clock cycle)",DAT_I,ADR_I,rTimeOut);
|
// $display("%d Theia Writes value: %h @ %d (Time to process pixel %d Clock cycle)",$time, DAT_I,ADR_I,rTimeOut);
|
|
|
|
|
if (Thingy == 0)
|
// if (Thingy == 0)
|
begin
|
// begin
|
$fwrite(file,"\n# %d %d\n",CurrentPixelRow,CurrentPixelCol);
|
|
$write(".");
|
// end
|
end
|
|
|
|
Thingy = Thingy + 1;
|
// Thingy = Thingy + 1;
|
if (CurrentPixelRow >= `RESOLUTION_WIDTH)
|
if (CurrentPixelCol >= (`RESOLUTION_WIDTH*3))
|
begin
|
begin
|
CurrentPixelRow = 0;
|
CurrentPixelCol = 0;
|
CurrentPixelCol = CurrentPixelCol + 1;
|
CurrentPixelRow = CurrentPixelRow + 1;
|
$display("]- %d (%d)",CurrentPixelCol,ADR_I);
|
$display("]- %d (%d)",CurrentPixelRow,ADR_I);
|
$write("[");
|
$write("[");
|
end
|
end
|
|
|
if (Thingy == 3)
|
// if (Thingy == 3)
|
|
// begin
|
|
CurrentPixelCol = CurrentPixelCol + 1;
|
|
if ( CurrentPixelCol % 3 == 0)
|
begin
|
begin
|
CurrentPixelRow = CurrentPixelRow + 1;
|
// $fwrite(file,"\n# %d %d\n",CurrentPixelRow,CurrentPixelCol);
|
Thingy = 0;
|
$write(".");
|
end
|
end
|
|
//Thingy = 0;
|
|
// end
|
rTimeOut = 0;
|
rTimeOut = 0;
|
R = ((DAT_I >> (`SCALE-8)) > 255) ? 255 : (DAT_I >> (`SCALE-8));
|
R = ((DAT_I >> (`SCALE-8)) > 255) ? 255 : (DAT_I >> (`SCALE-8));
|
$fwrite(file,"%d " , R );
|
rScreen[ ADR_I ] = R;
|
|
// $fwrite(file,"%d " , R );
|
|
|
end
|
end
|
|
|
|
|
ACK_O = 1;
|
ACK_O = 1;
|
|
|
if (CurrentPixelCol >= `RESOLUTION_HEIGHT)
|
// if (CurrentPixelRow >= `RESOLUTION_HEIGHT)
|
|
if (wDone)
|
WBSNextState = `WBS_DONE;
|
WBSNextState = `WBS_DONE;
|
else
|
else
|
WBSNextState = `WBS_MOINTOR_STB_I_NEG;
|
WBSNextState = `WBS_MOINTOR_STB_I_NEG;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
| Line 416... |
Line 430... |
WBSNextState = `WBS_MOINTOR_STB_I_NEG;
|
WBSNextState = `WBS_MOINTOR_STB_I_NEG;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
`WBS_DONE:
|
`WBS_DONE:
|
begin
|
begin
|
|
for (j = 0; j < `RESOLUTION_WIDTH; j = j+1)
|
|
begin
|
|
|
|
for (i = 0; i < `RESOLUTION_HEIGHT*3; i = i +1)
|
|
begin
|
|
|
|
$fwrite(file,"%d " , rScreen[i+j*`RESOLUTION_WIDTH*3] );
|
|
if ((i %3) == 0)
|
|
$fwrite(file,"\n# %d %d\n",i,j);
|
|
|
|
end
|
|
end
|
$display("RESOLUTION_WIDTH = %d,RESOLUTION_HEIGHT= %d",
|
$display("RESOLUTION_WIDTH = %d,RESOLUTION_HEIGHT= %d",
|
`RESOLUTION_WIDTH,`RESOLUTION_HEIGHT);
|
`RESOLUTION_WIDTH,`RESOLUTION_HEIGHT);
|
$display("ADR_I = %d\n",ADR_I);
|
$display("ADR_I = %d\n",ADR_I);
|
`LOGME"RENDER COMPLETE");
|
`LOGME"RENDER COMPLETE");
|
`LOGME"Closing File");
|
`LOGME"Closing File");
|
| Line 458... |
Line 484... |
`define WBM_ACK_DATA_PHASE2 9
|
`define WBM_ACK_DATA_PHASE2 9
|
`define WBM_SEND_DATA_PHASE3 10
|
`define WBM_SEND_DATA_PHASE3 10
|
`define WBM_ACK_DATA_PHASE3 11
|
`define WBM_ACK_DATA_PHASE3 11
|
`define WBM_END_DATA_WRITE_CYCLE 12
|
`define WBM_END_DATA_WRITE_CYCLE 12
|
`define WBM_DONE 13
|
`define WBM_DONE 13
|
|
`define WBM_CONFIGURE_CORE0_PHASE1 14
|
|
`define WBM_ACK_CONFIGURE_CORE0_PHASE1 15
|
|
`define WBM_CONFIGURE_CORE0_PHASE2 16
|
|
`define WBM_ACK_CONFIGURE_CORE0_PHASE2 17
|
|
`define WBM_CONFIGURE_CORE0_PHASE3 18
|
|
`define WBM_ACK_CONFIGURE_CORE0_PHASE3 19
|
|
`define WBM_CONFIGURE_CORE1_PHASE1 20
|
|
`define WBM_ACK_CONFIGURE_CORE1_PHASE1 21
|
|
`define WBM_CONFIGURE_CORE1_PHASE2 22
|
|
`define WBM_ACK_CONFIGURE_CORE1_PHASE2 23
|
|
`define WBM_CONFIGURE_CORE1_PHASE3 24
|
|
`define WBM_ACK_CONFIGURE_CORE1_PHASE3 25
|
|
`define WBM_END_CORE0_WRITE_CYCLE 26
|
|
`define WBM_END_CORE1_WRITE_CYCLE 27
|
|
|
|
|
reg[31:0] rInstructionPointer;
|
reg[31:0] rInstructionPointer;
|
reg[31:0] rAddressToSend;
|
reg[31:0] rAddressToSend;
|
reg[31:0] rDataAddress;
|
reg[31:0] rDataAddress;
|
reg[31:0] rDataPointer;
|
reg[31:0] rDataPointer;
|
|
|
reg IncIP,IncIA,IncDP;
|
reg IncIP,IncIA,IncDP;
|
|
reg rPrepateWriteAddressForNextCore;
|
reg rClearOutAddress;
|
reg rClearOutAddress;
|
//-----------------------------------------------------
|
//-----------------------------------------------------
|
always @ (posedge Clock or posedge rClearOutAddress)
|
always @ (posedge Clock or posedge rClearOutAddress)
|
begin
|
begin
|
|
|
| Line 476... |
Line 518... |
rAddressToSend = rAddressToSend + 1;
|
rAddressToSend = rAddressToSend + 1;
|
else if (rClearOutAddress)
|
else if (rClearOutAddress)
|
begin
|
begin
|
if (TGA_O == `TAG_INSTRUCTION_ADDRESS_TYPE)
|
if (TGA_O == `TAG_INSTRUCTION_ADDRESS_TYPE)
|
rAddressToSend = {16'd1,16'd0};
|
rAddressToSend = {16'd1,16'd0};
|
|
else if (rPrepateWriteAddressForNextCore)
|
|
rAddressToSend = `CREG_PIXEL_2D_INITIAL_POSITION;
|
else
|
else
|
rAddressToSend = 0;
|
rAddressToSend = 0;
|
end
|
end
|
|
|
|
|
| Line 569... |
Line 613... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 0;
|
MST_O <= 0;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 1;
|
rResetDp <= 1;
|
rClearOutAddress <= 1;
|
rClearOutAddress <= 1;
|
|
rCoreSelect <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
if (Reset == 0)
|
if (Reset == 0)
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
|
else
|
else
|
WBMNextState <= `WBM_AFTER_RESET;
|
WBMNextState <= `WBM_AFTER_RESET;
|
| Line 596... |
Line 643... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 1;
|
rResetDp <= 1;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
|
if ( ACK_I )
|
if ( ACK_I )
|
WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE1;
|
WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE1;
|
else
|
else
|
| Line 619... |
Line 668... |
IncIA <= 0; //leave the instruction write address the same
|
IncIA <= 0; //leave the instruction write address the same
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 1;
|
rResetDp <= 1;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
if (ACK_I == 0)
|
if (ACK_I == 0)
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE2;
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE2;
|
else
|
else
|
WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE1;
|
WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE1;
|
| Line 639... |
Line 691... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 1;
|
rResetDp <= 1;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
|
if ( ACK_I )
|
if ( ACK_I )
|
WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE2;
|
WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE2;
|
else
|
else
|
| Line 659... |
Line 714... |
STB_O <= 0; //*
|
STB_O <= 0; //*
|
|
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 1;
|
rResetDp <= 1;
|
|
rCoreSelect <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
if (rInstructionPointer >= rInstructionBuffer[0])
|
if (rInstructionPointer >= rInstructionBuffer[0])
|
begin
|
begin
|
IncIA <= 0;//*
|
IncIA <= 0;//*
|
rClearOutAddress <= 1;
|
rClearOutAddress <= 1;
|
| Line 690... |
Line 746... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
if ( ACK_I )
|
if ( ACK_I )
|
WBMNextState <= `WBM_ACK_DATA_PHASE1;
|
WBMNextState <= `WBM_ACK_DATA_PHASE1;
|
else
|
else
|
WBMNextState <= `WBM_SEND_DATA_PHASE1;
|
WBMNextState <= `WBM_SEND_DATA_PHASE1;
|
| Line 713... |
Line 770... |
IncIA <= 0; //leave the instruction write address the same
|
IncIA <= 0; //leave the instruction write address the same
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
if (ACK_I == 0)
|
if (ACK_I == 0)
|
WBMNextState <= `WBM_SEND_DATA_PHASE2;
|
WBMNextState <= `WBM_SEND_DATA_PHASE2;
|
else
|
else
|
WBMNextState <= `WBM_ACK_DATA_PHASE1;
|
WBMNextState <= `WBM_ACK_DATA_PHASE1;
|
| Line 733... |
Line 793... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
if ( ACK_I )
|
if ( ACK_I )
|
WBMNextState <= `WBM_ACK_DATA_PHASE2;
|
WBMNextState <= `WBM_ACK_DATA_PHASE2;
|
else
|
else
|
WBMNextState <= `WBM_SEND_DATA_PHASE2;
|
WBMNextState <= `WBM_SEND_DATA_PHASE2;
|
| Line 754... |
Line 816... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;//*
|
IncDP <= 0;//*
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
if (ACK_I == 0)
|
if (ACK_I == 0)
|
WBMNextState <= `WBM_SEND_DATA_PHASE3;
|
WBMNextState <= `WBM_SEND_DATA_PHASE3;
|
else
|
else
|
WBMNextState <= `WBM_ACK_DATA_PHASE2;
|
WBMNextState <= `WBM_ACK_DATA_PHASE2;
|
| Line 775... |
Line 840... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
if ( ACK_I )
|
if ( ACK_I )
|
WBMNextState <= `WBM_ACK_DATA_PHASE3;
|
WBMNextState <= `WBM_ACK_DATA_PHASE3;
|
else
|
else
|
WBMNextState <= `WBM_SEND_DATA_PHASE3;
|
WBMNextState <= `WBM_SEND_DATA_PHASE3;
|
| Line 796... |
Line 863... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 1;//*
|
IncDP <= 1;//*
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
WBMNextState <= `WBM_END_DATA_WRITE_CYCLE;
|
WBMNextState <= `WBM_END_DATA_WRITE_CYCLE;
|
|
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
| Line 813... |
Line 883... |
IncIA <= 1;//*
|
IncIA <= 1;//*
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= `SELECT_ALL_CORES;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if (rDataPointer > 3*5)//wConfigurationPacketSize*3)
|
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
|
|
else
|
|
WBMNextState <= `WBM_SEND_DATA_PHASE1;
|
|
|
|
end
|
|
//----------------------------------------
|
|
`WBM_CONFIGURE_CORE0_PHASE1:
|
|
begin
|
|
|
|
WE_O <= 1; //Indicate write cycle
|
|
CYC_O <= 1; //Start of the cycle
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0001;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE1;
|
|
else
|
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_ACK_CONFIGURE_CORE0_PHASE1:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
|
// IncIP <= 1; //* //Increment local inst pointer to send the next 32 bits
|
|
IncIA <= 0; //leave the instruction write address the same
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0001;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if (ACK_I == 0)
|
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE2;
|
|
else
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE1;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_CONFIGURE_CORE0_PHASE2:
|
|
begin
|
|
WE_O <= 1; //Indicate write cycle
|
|
CYC_O <= 1; //Start of the cycle
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0001;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE2;
|
|
else
|
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE2;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_ACK_CONFIGURE_CORE0_PHASE2:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
|
// IncIP <= 1; //* //Increment local inst pointer to send the next 32 bits
|
|
IncIA <= 0; //leave the instruction write address the same
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0001;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if (ACK_I == 0)
|
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE3;
|
|
else
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE2;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_CONFIGURE_CORE0_PHASE3:
|
|
begin
|
|
WE_O <= 1; //Indicate write cycle
|
|
CYC_O <= 1; //Start of the cycle
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0001;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE3;
|
|
else
|
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE3;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_ACK_CONFIGURE_CORE0_PHASE3:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
|
// IncIP <= 1; //* //Increment local inst pointer to send the next 32 bits
|
|
IncIA <= 0; //leave the instruction write address the same
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0001;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if (ACK_I == 0)
|
|
WBMNextState <= `WBM_END_CORE0_WRITE_CYCLE;
|
|
else
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE3;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_END_CORE0_WRITE_CYCLE:
|
|
begin
|
|
WE_O <= 0;
|
|
CYC_O <= 0; //*
|
|
TGC_O <= 0;
|
|
TGA_O <= 0;
|
|
STB_O <= 0;
|
|
IncIA <= 1;//*
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
|
|
rCoreSelect <= 4'b0001;
|
|
rRenderEnable <= 0;
|
|
|
|
|
|
if (rDataPointer > 3*7)
|
|
begin
|
|
rClearOutAddress <= 1;
|
|
rPrepateWriteAddressForNextCore <= 1;
|
|
WBMNextState <= `WBM_CONFIGURE_CORE1_PHASE1;
|
|
end
|
|
else
|
|
begin
|
|
rClearOutAddress <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
|
|
end
|
|
|
|
end
|
|
|
|
|
|
//----------------------------------------
|
|
//Ok so from this point we configure CORE,
|
|
//we are going to configure the register:
|
|
//CREG_PIXEL_2D_INITIAL_POSITION and CREG_PIXEL_2D_FINAL_POSITION
|
|
//Since we incremented our Write Address pointer from the Core0 config,
|
|
//then now we need to make point to CREG_PIXEL_2D_INITIAL_POSITION again
|
|
//ans repeat the process for CORE1
|
|
`WBM_CONFIGURE_CORE1_PHASE1:
|
|
begin
|
|
|
|
WE_O <= 1; //Indicate write cycle
|
|
CYC_O <= 1; //Start of the cycle
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0010;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE1_PHASE1;
|
|
else
|
|
WBMNextState <= `WBM_CONFIGURE_CORE1_PHASE1;
|
|
end
|
|
//----------------------------------------
|
|
|
|
`WBM_ACK_CONFIGURE_CORE1_PHASE1:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
|
// IncIP <= 1; //* //Increment local inst pointer to send the next 32 bits
|
|
IncIA <= 0; //leave the instruction write address the same
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0010;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if (ACK_I == 0)
|
|
WBMNextState <= `WBM_CONFIGURE_CORE1_PHASE2;
|
|
else
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE1_PHASE1;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_CONFIGURE_CORE1_PHASE2:
|
|
begin
|
|
WE_O <= 1; //Indicate write cycle
|
|
CYC_O <= 1; //Start of the cycle
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0010;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE1_PHASE2;
|
|
else
|
|
WBMNextState <= `WBM_CONFIGURE_CORE1_PHASE2;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_ACK_CONFIGURE_CORE1_PHASE2:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
|
// IncIP <= 1; //* //Increment local inst pointer to send the next 32 bits
|
|
IncIA <= 0; //leave the instruction write address the same
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0010;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if (ACK_I == 0)
|
|
WBMNextState <= `WBM_CONFIGURE_CORE1_PHASE3;
|
|
else
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE1_PHASE2;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_CONFIGURE_CORE1_PHASE3:
|
|
begin
|
|
WE_O <= 1; //Indicate write cycle
|
|
CYC_O <= 1; //Start of the cycle
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0010;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE1_PHASE3;
|
|
else
|
|
WBMNextState <= `WBM_CONFIGURE_CORE1_PHASE3;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_ACK_CONFIGURE_CORE1_PHASE3:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
|
// IncIP <= 1; //* //Increment local inst pointer to send the next 32 bits
|
|
IncIA <= 0; //leave the instruction write address the same
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0010;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if (ACK_I == 0)
|
|
WBMNextState <= `WBM_END_CORE1_WRITE_CYCLE;
|
|
else
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE1_PHASE3;
|
|
end
|
|
|
|
|
|
//----------------------------------------
|
|
`WBM_END_CORE1_WRITE_CYCLE:
|
|
begin
|
|
WE_O <= 0;
|
|
CYC_O <= 0; //*
|
|
TGC_O <= 0;
|
|
TGA_O <= 0;
|
|
STB_O <= 0;
|
|
IncIA <= 1;//*
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0010;
|
|
rRenderEnable <= 0;
|
|
|
|
|
if (rDataPointer > wConfigurationPacketSize*3)
|
if (rDataPointer > 3*10)
|
|
begin
|
|
rPrepateWriteAddressForNextCore <= 1;
|
WBMNextState <= `WBM_DONE;
|
WBMNextState <= `WBM_DONE;
|
|
end
|
else
|
else
|
WBMNextState <= `WBM_SEND_DATA_PHASE1;
|
begin
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
WBMNextState <= `WBM_CONFIGURE_CORE1_PHASE1;
|
|
end
|
|
|
end
|
end
|
|
|
//----------------------------------------
|
//----------------------------------------
|
|
|
| Line 838... |
Line 1259... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 0;
|
MST_O <= 0;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 1;
|
rResetDp <= 1;
|
rClearOutAddress <= 1;
|
rClearOutAddress <= 1;
|
|
rCoreSelect <= 4'b0010;
|
|
rRenderEnable <= 4'b0011;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
WBMNextState <= `WBM_DONE;
|
WBMNextState <= `WBM_DONE;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
|
|
