| Line 61... |
Line 61... |
`define RESOLUTION_HEIGHT (rSceneParameters[13] >> `SCALE)
|
`define RESOLUTION_HEIGHT (rSceneParameters[13] >> `SCALE)
|
`define RAYI_TASK 1
|
`define RAYI_TASK 1
|
`define DELTA_ROW (32'h1 << `SCALE)
|
`define DELTA_ROW (32'h1 << `SCALE)
|
`define DELTA_COL (32'h1 << `SCALE)
|
`define DELTA_COL (32'h1 << `SCALE)
|
|
|
`define SELECT_ALL_CORES `MAX_CORES'b0011;
|
`define SELECT_ALL_CORES `MAX_CORES'b1111;
|
module TestBench_Theia;
|
module TestBench_Theia;
|
|
|
|
|
//------------------------------------------------------------------------
|
//------------------------------------------------------------------------
|
//**WARNING: Declare all of your varaibles at the begining
|
//**WARNING: Declare all of your varaibles at the begining
|
| Line 109... |
Line 109... |
|
|
|
|
integer file, log, r, a, b;
|
integer file, log, r, a, b;
|
|
|
|
|
reg [31:0] rSceneParameters[31:0];
|
reg [31:0] rSceneParameters[64:0];
|
reg [31:0] rVertexBuffer[6000:0];
|
reg [31:0] rVertexBuffer[6000:0];
|
reg [31:0] rInstructionBuffer[512:0];
|
reg [31:0] rInstructionBuffer[512:0];
|
`define TEXTURE_BUFFER_SIZE (256*256*3)
|
`define TEXTURE_BUFFER_SIZE (256*256*3)
|
reg [31:0] rTextures[`TEXTURE_BUFFER_SIZE:0]; //Lets asume we use 256*256 textures
|
reg [31:0] rTextures[`TEXTURE_BUFFER_SIZE:0]; //Lets asume we use 256*256 textures
|
|
|
| Line 132... |
Line 132... |
|
|
|
|
|
|
reg MST_O;
|
reg MST_O;
|
//---------------------------------------------------------------
|
//---------------------------------------------------------------
|
|
reg rIncCoreSelect;
|
|
wire [`MAX_CORES-1:0] wCoreSelect;
|
|
CIRCULAR_SHIFTLEFT_POSEDGE_EX # (`MAX_CORES ) SHF1
|
|
(
|
|
.Clock( Clock ),
|
|
.Reset( Reset ),
|
|
.Initial(`MAX_CORES'b1),
|
|
.Enable(rIncCoreSelect),
|
|
.O(wCoreSelect)
|
|
);
|
|
|
|
|
wire [3:0] CYC_I,GNT_O;
|
wire [3:0] CYC_I,GNT_O;
|
wire wDone;
|
wire wDone;
|
reg [`MAX_CORES-1:0] rCoreSelect,rRenderEnable;
|
reg [`MAX_CORES-1:0] rCoreSelectMask,rRenderEnable;
|
|
|
THEIA GPU
|
THEIA GPU
|
(
|
(
|
.CLK_I( Clock ),
|
.CLK_I( Clock ),
|
.RST_I( Reset ),
|
.RST_I( Reset ),
|
| Line 156... |
Line 167... |
.TGA_I( TGA_O ),
|
.TGA_I( TGA_O ),
|
.ACK_O( ACK_I ),
|
.ACK_O( ACK_I ),
|
.ADR_I( ADR_O ),
|
.ADR_I( ADR_O ),
|
.DAT_O( DAT_I ),
|
.DAT_O( DAT_I ),
|
.WE_I( WE_O ),
|
.WE_I( WE_O ),
|
.SEL_I( rCoreSelect ),//4'b0001 ),
|
.SEL_I( wCoreSelect | rCoreSelectMask),//4'b0001 ),
|
.STB_I( STB_O ),
|
.STB_I( STB_O ),
|
.TGA_O(TGA_I),
|
.TGA_O(TGA_I),
|
|
|
//Control register
|
//Control register
|
.CREG_I( rControlRegister[0][15:0] ),
|
.CREG_I( rControlRegister[0][15:0] ),
|
| Line 356... |
Line 367... |
if (rConvertedTextureAddress >= `TEXTURE_BUFFER_SIZE)
|
if (rConvertedTextureAddress >= `TEXTURE_BUFFER_SIZE)
|
rConvertedTextureAddress = `TEXTURE_BUFFER_SIZE-1;
|
rConvertedTextureAddress = `TEXTURE_BUFFER_SIZE-1;
|
|
|
|
|
rSlaveData_O = rTextures[ rConvertedTextureAddress ];
|
rSlaveData_O = rTextures[ rConvertedTextureAddress ];
|
`ifdef DEBUG
|
`ifdef DEBUG_WBM
|
|
|
`LOGME"WB SLAVE: MASTER Requested read from texture address: %h (%d)Data = %h \n",rAddress, rConvertedTextureAddress,DAT_O );
|
`LOGME"WB SLAVE: MASTER Requested read from texture address: %h (%d)Data = %h \n",rAddress, rConvertedTextureAddress,DAT_O );
|
`endif
|
`endif
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// Thingy = 0; //THIS IS NOT RE-ENTRANT!!!
|
// Thingy = 0; //THIS IS NOT RE-ENTRANT!!!
|
rSlaveData_O = rVertexBuffer[ rAddress ];
|
rSlaveData_O = rVertexBuffer[ rAddress ];
|
`ifdef DEBUG
|
`ifdef DEBUG_WBM
|
`LOGME"WB SLAVE: MASTER Requested read from vertex address: %h Data = %h\n",rAddress,DAT_O);
|
`LOGME"WB SLAVE: MASTER Requested read from vertex address: %h Data = %h\n",rAddress,DAT_O);
|
`endif
|
`endif
|
end
|
end
|
|
|
end
|
end
|
| Line 499... |
Line 510... |
`define WBM_CONFIGURE_CORE1_PHASE3 24
|
`define WBM_CONFIGURE_CORE1_PHASE3 24
|
`define WBM_ACK_CONFIGURE_CORE1_PHASE3 25
|
`define WBM_ACK_CONFIGURE_CORE1_PHASE3 25
|
`define WBM_END_CORE0_WRITE_CYCLE 26
|
`define WBM_END_CORE0_WRITE_CYCLE 26
|
`define WBM_END_CORE1_WRITE_CYCLE 27
|
`define WBM_END_CORE1_WRITE_CYCLE 27
|
|
|
|
`define WBM_CONFIGURE_CORE2_PHASE1 28
|
|
`define WBM_ACK_CONFIGURE_CORE2_PHASE1 29
|
|
`define WBM_CONFIGURE_CORE2_PHASE2 30
|
|
`define WBM_ACK_CONFIGURE_CORE2_PHASE2 31
|
|
`define WBM_CONFIGURE_CORE2_PHASE3 32
|
|
`define WBM_ACK_CONFIGURE_CORE2_PHASE3 33
|
|
`define WBM_CONFIGURE_CORE3_PHASE1 34
|
|
`define WBM_ACK_CONFIGURE_CORE3_PHASE1 35
|
|
`define WBM_CONFIGURE_CORE3_PHASE2 36
|
|
`define WBM_ACK_CONFIGURE_CORE3_PHASE2 37
|
|
`define WBM_CONFIGURE_CORE3_PHASE3 38
|
|
`define WBM_ACK_CONFIGURE_CORE3_PHASE3 39
|
|
`define WBM_END_CORE2_WRITE_CYCLE 40
|
|
`define WBM_END_CORE3_WRITE_CYCLE 41
|
|
`define WBM_CONFIGURE_NEXT_CORE 42
|
|
|
|
|
reg[31:0] rInstructionPointer;
|
reg[31:0] rInstructionPointer;
|
reg[31:0] rAddressToSend;
|
reg[31:0] rAddressToSend;
|
reg[31:0] rDataAddress;
|
reg[31:0] rDataAddress;
|
reg[31:0] rDataPointer;
|
reg[31:0] rDataPointer;
|
| Line 551... |
Line 578... |
else if (rResetDp)
|
else if (rResetDp)
|
rDataPointer = 32'b0;
|
rDataPointer = 32'b0;
|
|
|
|
|
end
|
end
|
|
|
|
reg rIncPacketCount;
|
|
reg [`WIDTH-1:0] rPacketCount;
|
|
|
|
always @ (posedge Clock)
|
|
begin
|
|
if (Reset)
|
|
rPacketCount = 0;
|
|
else
|
|
begin
|
|
if ( rIncPacketCount )
|
|
rPacketCount = rPacketCount + 1;
|
|
end
|
|
end
|
//-----------------------------------------------------
|
//-----------------------------------------------------
|
|
|
|
|
|
|
|
|
| Line 613... |
Line 654... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 0;
|
MST_O <= 0;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 1;
|
rResetDp <= 1;
|
rClearOutAddress <= 1;
|
rClearOutAddress <= 1;
|
rCoreSelect <= `SELECT_ALL_CORES;
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
if (Reset == 0)
|
if (Reset == 0)
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
|
else
|
else
|
WBMNextState <= `WBM_AFTER_RESET;
|
WBMNextState <= `WBM_AFTER_RESET;
|
| Line 643... |
Line 685... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 1;
|
rResetDp <= 1;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= `SELECT_ALL_CORES;
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
if ( ACK_I )
|
if ( ACK_I )
|
WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE1;
|
WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE1;
|
else
|
else
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE1;
|
| Line 668... |
Line 710... |
IncIA <= 0; //leave the instruction write address the same
|
IncIA <= 0; //leave the instruction write address the same
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 1;
|
rResetDp <= 1;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= `SELECT_ALL_CORES;
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
if (ACK_I == 0)
|
if (ACK_I == 0)
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE2;
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE2;
|
else
|
else
|
WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE1;
|
WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE1;
|
| Line 691... |
Line 734... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 1;
|
rResetDp <= 1;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= `SELECT_ALL_CORES;
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
if ( ACK_I )
|
if ( ACK_I )
|
WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE2;
|
WBMNextState <= `WBM_ACK_INSTRUCTION_PHASE2;
|
else
|
else
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE2;
|
WBMNextState <= `WBM_WRITE_INSTRUCTION_PHASE2;
|
| Line 714... |
Line 757... |
STB_O <= 0; //*
|
STB_O <= 0; //*
|
|
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 1;
|
rResetDp <= 1;
|
rCoreSelect <= `SELECT_ALL_CORES;
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
if (rInstructionPointer >= rInstructionBuffer[0])
|
if (rInstructionPointer >= rInstructionBuffer[0])
|
begin
|
begin
|
IncIA <= 0;//*
|
IncIA <= 0;//*
|
rClearOutAddress <= 1;
|
rClearOutAddress <= 1;
|
| Line 740... |
Line 785... |
WE_O <= 1; //Indicate write cycle
|
WE_O <= 1; //Indicate write cycle
|
CYC_O <= 1; //Start of the cycle
|
CYC_O <= 1; //Start of the cycle
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= `SELECT_ALL_CORES;
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
if ( ACK_I )
|
if ( ACK_I )
|
WBMNextState <= `WBM_ACK_DATA_PHASE1;
|
WBMNextState <= `WBM_ACK_DATA_PHASE1;
|
else
|
else
|
WBMNextState <= `WBM_SEND_DATA_PHASE1;
|
WBMNextState <= `WBM_SEND_DATA_PHASE1;
|
| Line 770... |
Line 816... |
IncIA <= 0; //leave the instruction write address the same
|
IncIA <= 0; //leave the instruction write address the same
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= `SELECT_ALL_CORES;
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
|
if (ACK_I == 0)
|
if (ACK_I == 0)
|
WBMNextState <= `WBM_SEND_DATA_PHASE2;
|
WBMNextState <= `WBM_SEND_DATA_PHASE2;
|
else
|
else
|
WBMNextState <= `WBM_ACK_DATA_PHASE1;
|
WBMNextState <= `WBM_ACK_DATA_PHASE1;
|
| Line 793... |
Line 842... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= `SELECT_ALL_CORES;
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
if ( ACK_I )
|
if ( ACK_I )
|
WBMNextState <= `WBM_ACK_DATA_PHASE2;
|
WBMNextState <= `WBM_ACK_DATA_PHASE2;
|
else
|
else
|
WBMNextState <= `WBM_SEND_DATA_PHASE2;
|
WBMNextState <= `WBM_SEND_DATA_PHASE2;
|
| Line 816... |
Line 867... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;//*
|
IncDP <= 0;//*
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= `SELECT_ALL_CORES;
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
|
if (ACK_I == 0)
|
if (ACK_I == 0)
|
WBMNextState <= `WBM_SEND_DATA_PHASE3;
|
WBMNextState <= `WBM_SEND_DATA_PHASE3;
|
else
|
else
|
WBMNextState <= `WBM_ACK_DATA_PHASE2;
|
WBMNextState <= `WBM_ACK_DATA_PHASE2;
|
| Line 840... |
Line 894... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= `SELECT_ALL_CORES;
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
|
if ( ACK_I )
|
if ( ACK_I )
|
WBMNextState <= `WBM_ACK_DATA_PHASE3;
|
WBMNextState <= `WBM_ACK_DATA_PHASE3;
|
else
|
else
|
WBMNextState <= `WBM_SEND_DATA_PHASE3;
|
WBMNextState <= `WBM_SEND_DATA_PHASE3;
|
| Line 863... |
Line 920... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 1;//*
|
IncDP <= 1;//*
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= `SELECT_ALL_CORES;
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
|
WBMNextState <= `WBM_END_DATA_WRITE_CYCLE;
|
WBMNextState <= `WBM_END_DATA_WRITE_CYCLE;
|
|
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
| Line 883... |
Line 943... |
IncIA <= 1;//*
|
IncIA <= 1;//*
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= `SELECT_ALL_CORES;
|
rCoreSelectMask <= `SELECT_ALL_CORES;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
|
|
if (rDataPointer > 3*5)//wConfigurationPacketSize*3)
|
if (rDataPointer > 3*5)//wConfigurationPacketSize*3)
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
|
else
|
else
|
WBMNextState <= `WBM_SEND_DATA_PHASE1;
|
WBMNextState <= `WBM_SEND_DATA_PHASE1;
|
| Line 902... |
Line 965... |
WE_O <= 1; //Indicate write cycle
|
WE_O <= 1; //Indicate write cycle
|
CYC_O <= 1; //Start of the cycle
|
CYC_O <= 1; //Start of the cycle
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= 4'b0001;
|
|
|
rIncCoreSelect <= 0;
|
|
rCoreSelectMask <= 0;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
if ( ACK_I )
|
if ( ACK_I )
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE1;
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE1;
|
else
|
else
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
|
| Line 925... |
Line 991... |
WE_O <= 1;
|
WE_O <= 1;
|
CYC_O <= 1;
|
CYC_O <= 1;
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
// IncIP <= 1; //* //Increment local inst pointer to send the next 32 bits
|
|
IncIA <= 0; //leave the instruction write address the same
|
IncIA <= 0; //leave the instruction write address the same
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= 4'b0001;
|
rIncCoreSelect <= 0;
|
|
rCoreSelectMask <= 0;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
if (ACK_I == 0)
|
if (ACK_I == 0)
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE2;
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE2;
|
else
|
else
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE1;
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE1;
|
| Line 948... |
Line 1016... |
WE_O <= 1; //Indicate write cycle
|
WE_O <= 1; //Indicate write cycle
|
CYC_O <= 1; //Start of the cycle
|
CYC_O <= 1; //Start of the cycle
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= 4'b0001;
|
|
|
rIncCoreSelect <= 0;
|
|
rCoreSelectMask <= 0;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
if ( ACK_I )
|
if ( ACK_I )
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE2;
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE2;
|
else
|
else
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE2;
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE2;
|
| Line 971... |
Line 1041... |
WE_O <= 1;
|
WE_O <= 1;
|
CYC_O <= 1;
|
CYC_O <= 1;
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
// IncIP <= 1; //* //Increment local inst pointer to send the next 32 bits
|
|
IncIA <= 0; //leave the instruction write address the same
|
IncIA <= 0; //leave the instruction write address the same
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= 4'b0001;
|
|
|
rIncCoreSelect <= 0;
|
|
rCoreSelectMask <= 0;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
if (ACK_I == 0)
|
if (ACK_I == 0)
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE3;
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE3;
|
else
|
else
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE2;
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE2;
|
| Line 994... |
Line 1066... |
WE_O <= 1; //Indicate write cycle
|
WE_O <= 1; //Indicate write cycle
|
CYC_O <= 1; //Start of the cycle
|
CYC_O <= 1; //Start of the cycle
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= 4'b0001;
|
rIncPacketCount <= 0;
|
|
|
|
|
|
rIncCoreSelect <= 0;
|
|
rCoreSelectMask <= 0;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
if ( ACK_I )
|
if ( ACK_I )
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE3;
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE3;
|
| Line 1017... |
Line 1092... |
WE_O <= 1;
|
WE_O <= 1;
|
CYC_O <= 1;
|
CYC_O <= 1;
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
// IncIP <= 1; //* //Increment local inst pointer to send the next 32 bits
|
|
IncIA <= 0; //leave the instruction write address the same
|
IncIA <= 0; //leave the instruction write address the same
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rCoreSelect <= 4'b0001;
|
|
|
rIncCoreSelect <= 0;
|
|
rCoreSelectMask <= 0;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
rIncPacketCount <= 1;
|
|
|
if (ACK_I == 0)
|
if (ACK_I == 0)
|
WBMNextState <= `WBM_END_CORE0_WRITE_CYCLE;
|
WBMNextState <= `WBM_END_CORE0_WRITE_CYCLE;
|
else
|
else
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE3;
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE0_PHASE3;
|
| Line 1044... |
Line 1121... |
STB_O <= 0;
|
STB_O <= 0;
|
IncIA <= 1;//*
|
IncIA <= 1;//*
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
|
rIncCoreSelect <= 0;
|
rCoreSelect <= 4'b0001;
|
rCoreSelectMask <= 0;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
if (rDataPointer > 3*7)
|
if ((rPacketCount %2) == 0) //Two packets per Core
|
begin
|
begin
|
rClearOutAddress <= 1;
|
rClearOutAddress <= 1;
|
rPrepateWriteAddressForNextCore <= 1;
|
rPrepateWriteAddressForNextCore <= 1;
|
WBMNextState <= `WBM_CONFIGURE_CORE1_PHASE1;
|
WBMNextState <= `WBM_CONFIGURE_NEXT_CORE;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rClearOutAddress <= 0;
|
rClearOutAddress <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
|
end
|
end
|
|
|
end
|
end
|
|
|
|
//------------------------------------------
|
|
|
//----------------------------------------
|
`WBM_CONFIGURE_NEXT_CORE:
|
//Ok so from this point we configure CORE,
|
|
//we are going to configure the register:
|
|
//CREG_PIXEL_2D_INITIAL_POSITION and CREG_PIXEL_2D_FINAL_POSITION
|
|
//Since we incremented our Write Address pointer from the Core0 config,
|
|
//then now we need to make point to CREG_PIXEL_2D_INITIAL_POSITION again
|
|
//ans repeat the process for CORE1
|
|
`WBM_CONFIGURE_CORE1_PHASE1:
|
|
begin
|
|
|
|
WE_O <= 1; //Indicate write cycle
|
|
CYC_O <= 1; //Start of the cycle
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0010;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE1_PHASE1;
|
|
else
|
|
WBMNextState <= `WBM_CONFIGURE_CORE1_PHASE1;
|
|
end
|
|
//----------------------------------------
|
|
|
|
`WBM_ACK_CONFIGURE_CORE1_PHASE1:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
|
// IncIP <= 1; //* //Increment local inst pointer to send the next 32 bits
|
|
IncIA <= 0; //leave the instruction write address the same
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0010;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if (ACK_I == 0)
|
|
WBMNextState <= `WBM_CONFIGURE_CORE1_PHASE2;
|
|
else
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE1_PHASE1;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_CONFIGURE_CORE1_PHASE2:
|
|
begin
|
|
WE_O <= 1; //Indicate write cycle
|
|
CYC_O <= 1; //Start of the cycle
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0010;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE1_PHASE2;
|
|
else
|
|
WBMNextState <= `WBM_CONFIGURE_CORE1_PHASE2;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_ACK_CONFIGURE_CORE1_PHASE2:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
|
// IncIP <= 1; //* //Increment local inst pointer to send the next 32 bits
|
|
IncIA <= 0; //leave the instruction write address the same
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0010;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if (ACK_I == 0)
|
|
WBMNextState <= `WBM_CONFIGURE_CORE1_PHASE3;
|
|
else
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE1_PHASE2;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_CONFIGURE_CORE1_PHASE3:
|
|
begin
|
|
WE_O <= 1; //Indicate write cycle
|
|
CYC_O <= 1; //Start of the cycle
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE; //TAG CYCLE: 10 indicated multiple write Cycle
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE; //TAG Address: 01 means instruction address type.
|
|
STB_O <= ~ACK_I; //Start of phase (you put this in zero to introduce wait cycles)
|
|
// IncIP <= 0;
|
|
IncIA <= 0;
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0010;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if ( ACK_I )
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE1_PHASE3;
|
|
else
|
|
WBMNextState <= `WBM_CONFIGURE_CORE1_PHASE3;
|
|
end
|
|
//----------------------------------------
|
|
`WBM_ACK_CONFIGURE_CORE1_PHASE3:
|
|
begin
|
|
WE_O <= 1;
|
|
CYC_O <= 1;
|
|
TGC_O <= `TAG_BLOCK_WRITE_CYCLE;
|
|
TGA_O <= `TAG_DATA_ADDRESS_TYPE;
|
|
STB_O <= 0; //* //Negate STB_O in response to ACK_I
|
|
// IncIP <= 1; //* //Increment local inst pointer to send the next 32 bits
|
|
IncIA <= 0; //leave the instruction write address the same
|
|
MST_O <= 1;
|
|
IncDP <= 0;
|
|
rResetDp <= 0;
|
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0010;
|
|
rRenderEnable <= 0;
|
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
|
if (ACK_I == 0)
|
|
WBMNextState <= `WBM_END_CORE1_WRITE_CYCLE;
|
|
else
|
|
WBMNextState <= `WBM_ACK_CONFIGURE_CORE1_PHASE3;
|
|
end
|
|
|
|
|
|
//----------------------------------------
|
|
`WBM_END_CORE1_WRITE_CYCLE:
|
|
begin
|
begin
|
WE_O <= 0;
|
WE_O <= 0;
|
CYC_O <= 0; //*
|
CYC_O <= 0;
|
TGC_O <= 0;
|
TGC_O <= 0;
|
TGA_O <= 0;
|
TGA_O <= 0;
|
STB_O <= 0;
|
STB_O <= 0;
|
IncIA <= 1;//*
|
IncIA <= 0;
|
MST_O <= 1;
|
MST_O <= 1;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 0;
|
rResetDp <= 0;
|
rClearOutAddress <= 0;
|
|
rCoreSelect <= 4'b0010;
|
rCoreSelectMask <= 0;
|
|
rIncCoreSelect <= 1;
|
rRenderEnable <= 0;
|
rRenderEnable <= 0;
|
|
rIncPacketCount <= 0;
|
|
|
|
|
if (rDataPointer > 3*10)
|
if (wCoreSelect[`MAX_CORES-1] == 1)
|
begin
|
|
rPrepateWriteAddressForNextCore <= 1;
|
|
WBMNextState <= `WBM_DONE;
|
WBMNextState <= `WBM_DONE;
|
end
|
|
else
|
else
|
begin
|
WBMNextState <= `WBM_CONFIGURE_CORE0_PHASE1;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
WBMNextState <= `WBM_CONFIGURE_CORE1_PHASE1;
|
|
end
|
|
|
|
end
|
end
|
|
|
//----------------------------------------
|
|
|
|
|
|
|
//----------------------------------------
|
//Here everything is ready so just start!
|
//Here everything is ready so just start!
|
|
|
`WBM_DONE:
|
`WBM_DONE:
|
begin
|
begin
|
WE_O <= 0;
|
WE_O <= 0;
|
| Line 1259... |
Line 1187... |
IncIA <= 0;
|
IncIA <= 0;
|
MST_O <= 0;
|
MST_O <= 0;
|
IncDP <= 0;
|
IncDP <= 0;
|
rResetDp <= 1;
|
rResetDp <= 1;
|
rClearOutAddress <= 1;
|
rClearOutAddress <= 1;
|
rCoreSelect <= 4'b0010;
|
rCoreSelectMask <= 0;
|
rRenderEnable <= 4'b0011;
|
rRenderEnable <= 4'b1111;
|
rPrepateWriteAddressForNextCore <= 0;
|
rPrepateWriteAddressForNextCore <= 0;
|
|
|
WBMNextState <= `WBM_DONE;
|
WBMNextState <= `WBM_DONE;
|
end
|
end
|
//----------------------------------------
|
//----------------------------------------
|
