OpenCores
URL https://opencores.org/ocsvn/thor/thor/trunk

Subversion Repositories thor

[/] [thor/] [trunk/] [FT64v5/] [rtl/] [common/] [FT64_RSB.v] - Diff between revs 48 and 49

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 48 Rev 49
Line 54... Line 54...
output [AMSB:0] pc;
output [AMSB:0] pc;
 
 
parameter RSTPC = 32'hFFFC0100;
parameter RSTPC = 32'hFFFC0100;
integer n;
integer n;
reg [AMSB:0] ras [0:DEPTH-1];
reg [AMSB:0] ras [0:DEPTH-1];
reg [4:0] rasp;
reg [3:0] rasp;
assign pc = ras[rasp];
assign pc = ras[rasp];
 
reg [47:0] lasti0, lasti1;
 
 
always @(posedge clk)
always @(posedge clk)
if (rst) begin
if (rst) begin
    for (n = 0; n < 32; n = n + 1)
        lasti0 <= `NOP_INSN;
 
        lasti1 <= `NOP_INSN;
 
  for (n = 0; n < DEPTH; n = n + 1)
         ras[n] <= RSTPC;
         ras[n] <= RSTPC;
     rasp <= 5'd0;
  rasp <= 4'd0;
end
end
else begin
else begin
        if (fetchbuf0_v && fetchbuf1_v && (queued1 || queued2)) begin
        if (fetchbuf0_v && fetchbuf1_v && (queued1 || queued2)) begin
 
                // Make sure the instruction changed between clock cycles.
 
                lasti0 <= fetchbuf0_instr;
 
                lasti1 <= fetchbuf1_instr;
 
                if (fetchbuf0_instr != lasti0 || fetchbuf1_instr != lasti1) begin
        case(fetchbuf0_instr[`INSTRUCTION_OP])
        case(fetchbuf0_instr[`INSTRUCTION_OP])
        `JAL:
        `JAL:
                begin
                begin
                        // JAL LR,xxxx  assume call
                        // JAL LR,xxxx  assume call
                        if (fetchbuf0_instr[`INSTRUCTION_RB]==regLR) begin
                        if (fetchbuf0_instr[`INSTRUCTION_RB]==regLR) begin
                        ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + 32'd4;
                        ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);
                        rasp <= rasp - 4'd1;
                        rasp <= rasp - 4'd1;
                        end
                        end
                        // JAL r0,[r29] assume a ret
                        // JAL r0,[r29] assume a ret
                        else if (fetchbuf0_instr[`INSTRUCTION_RB]==5'd00 &&
                        else if (fetchbuf0_instr[`INSTRUCTION_RB]==5'd00 &&
                                         fetchbuf0_instr[`INSTRUCTION_RA]==regLR) begin
                                         fetchbuf0_instr[`INSTRUCTION_RA]==regLR) begin
                                rasp <= rasp + 4'd1;
                                rasp <= rasp + 4'd1;
                        end
                        end
                end
                end
        `CALL:
        `CALL:
            begin
            begin
                 ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + 32'd4;
                 ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);
                 rasp <= rasp - 4'd1;
                 rasp <= rasp - 4'd1;
            end
            end
        `RET:   begin
        `RET:   begin
                        $display("RSP: Added 1");
                        $display("RSP: Added 1");
                        rasp <= rasp + 4'd1;
                        rasp <= rasp + 4'd1;
                        end
                        end
        default:        ;
        default:        ;
        endcase
        endcase
        end
        end
 
        end
    else if (fetchbuf1_v && queued1)
    else if (fetchbuf1_v && queued1)
 
        lasti1 <= fetchbuf1_instr;
 
        if (fetchbuf1_instr != lasti1) begin
        case(fetchbuf1_instr[`INSTRUCTION_OP])
        case(fetchbuf1_instr[`INSTRUCTION_OP])
        `JAL:
        `JAL:
                if (fetchbuf1_instr[`INSTRUCTION_RB]==regLR) begin
                if (fetchbuf1_instr[`INSTRUCTION_RB]==regLR) begin
                 ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf1_pc + 32'd4;
                 ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf1_pc + (fetchbuf1_instr[6] ? 32'd6 : 32'd4);
                 rasp <= rasp - 4'd1;
                 rasp <= rasp - 4'd1;
                end
                end
                else if (fetchbuf1_instr[`INSTRUCTION_RB]==5'd00 &&
                else if (fetchbuf1_instr[`INSTRUCTION_RB]==5'd00 &&
                                 fetchbuf1_instr[`INSTRUCTION_RA]==regLR) begin
                                 fetchbuf1_instr[`INSTRUCTION_RA]==regLR) begin
                        rasp <= rasp + 4'd1;
                        rasp <= rasp + 4'd1;
                end
                end
        `CALL:
        `CALL:
            begin
            begin
                 ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf1_pc + 32'd4;
                 ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf1_pc + (fetchbuf1_instr[6] ? 32'd6 : 32'd4);
                 rasp <= rasp - 4'd1;
                 rasp <= rasp - 4'd1;
            end
            end
        `RET:   begin
        `RET:   begin
                        rasp <= rasp + 4'd1;
                        rasp <= rasp + 4'd1;
                        $display("RSP: Added 1");
                        $display("RSP: Added 1");
                        end
                        end
        default:        ;
        default:        ;
        endcase
        endcase
 
      end
    else if (fetchbuf0_v && queued1)
    else if (fetchbuf0_v && queued1)
 
        lasti0 <= fetchbuf0_instr;
 
        if (lasti0 != fetchbuf0_instr) begin
        case(fetchbuf0_instr[`INSTRUCTION_OP])
        case(fetchbuf0_instr[`INSTRUCTION_OP])
        `JAL:
        `JAL:
                if (fetchbuf0_instr[`INSTRUCTION_RB]==regLR) begin
                if (fetchbuf0_instr[`INSTRUCTION_RB]==regLR) begin
                 ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + 32'd4;
                 ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);
                 rasp <= rasp - 4'd1;
                 rasp <= rasp - 4'd1;
                end
                end
                else if (fetchbuf0_instr[`INSTRUCTION_RB]==5'd00 &&
                else if (fetchbuf0_instr[`INSTRUCTION_RB]==5'd00 &&
                                 fetchbuf0_instr[`INSTRUCTION_RA]==regLR) begin
                                 fetchbuf0_instr[`INSTRUCTION_RA]==regLR) begin
                        rasp <= rasp + 4'd1;
                        rasp <= rasp + 4'd1;
                end
                end
        `CALL:
        `CALL:
            begin
            begin
                 ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + 32'd4;
                 ras[((rasp-6'd1)&(DEPTH-1))] <= fetchbuf0_pc + (fetchbuf0_instr[6] ? 32'd6 : 32'd4);
                 rasp <= rasp - 4'd1;
                 rasp <= rasp - 4'd1;
            end
            end
        `RET:   begin
        `RET:   begin
                        $display("RSP: Added 1");
                        $display("RSP: Added 1");
                        rasp <= rasp + 4'd1;
                        rasp <= rasp + 4'd1;
                        end
                        end
        default:        ;
        default:        ;
        endcase
        endcase
 
      end
/*
/*
    if (stompedRets > 4'd0) begin
    if (stompedRets > 4'd0) begin
        $display("Stomped Rets: %d", stompedRets);
        $display("Stomped Rets: %d", stompedRets);
        rasp <= rasp - stompedRets;
        rasp <= rasp - stompedRets;
    end
    end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.