| Line 38... |
Line 38... |
output reg [4:0] id_o;
|
output reg [4:0] id_o;
|
output reg idv_o;
|
output reg idv_o;
|
|
|
parameter TRUE = 1'b1;
|
parameter TRUE = 1'b1;
|
parameter FALSE = 1'b0;
|
parameter FALSE = 1'b0;
|
|
// Memory access sizes
|
|
parameter byt = 3'd0;
|
|
parameter wyde = 3'd1;
|
|
parameter tetra = 3'd2;
|
|
parameter octa = 3'd3;
|
|
|
// Really IsPredictableBranch
|
// Really IsPredictableBranch
|
// Does not include BccR's
|
// Does not include BccR's
|
//function IsBranch;
|
//function IsBranch;
|
//input [47:0] isn;
|
//input [47:0] isn;
|
| Line 63... |
Line 68... |
|
|
|
|
reg IsALU;
|
reg IsALU;
|
always @*
|
always @*
|
case(instr[`INSTRUCTION_OP])
|
case(instr[`INSTRUCTION_OP])
|
`R2: if (instr[`INSTRUCTION_L2]==2'b00)
|
`R2:
|
|
if (instr[`INSTRUCTION_L2]==2'b00)
|
case(instr[`INSTRUCTION_S2])
|
case(instr[`INSTRUCTION_S2])
|
`VMOV: IsALU = TRUE;
|
`VMOV: IsALU = TRUE;
|
`RTI: IsALU = FALSE;
|
`RTI: IsALU = FALSE;
|
default: IsALU = TRUE;
|
default: IsALU = TRUE;
|
endcase
|
endcase
|
| Line 105... |
Line 111... |
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`R1: IsAlu0Only = TRUE;
|
`R1: IsAlu0Only = TRUE;
|
`SHIFTR,`SHIFT31,`SHIFT63:
|
`SHIFTR,`SHIFT31,`SHIFT63:
|
IsAlu0Only = TRUE;
|
IsAlu0Only = TRUE;
|
`MULU,`MULSU,`MUL,
|
`MULU,`MULSU,`MUL,
|
`DIVMODU,`DIVMODSU,`DIVMOD: IsAlu0Only = TRUE;
|
`MULUH,`MULSUH,`MULH,
|
|
`MODU,`MODSU,`MOD: IsAlu0Only = TRUE;
|
|
`DIVU,`DIVSU,`DIV: IsAlu0Only = TRUE;
|
`MIN,`MAX: IsAlu0Only = TRUE;
|
`MIN,`MAX: IsAlu0Only = TRUE;
|
default: IsAlu0Only = FALSE;
|
default: IsAlu0Only = FALSE;
|
endcase
|
endcase
|
else
|
else
|
IsAlu0Only = FALSE;
|
IsAlu0Only = FALSE;
|
| Line 214... |
Line 222... |
endcase
|
endcase
|
`ADDI,`DIVI,`MODI,`MULI:
|
`ADDI,`DIVI,`MODI,`MULI:
|
fnCanException = `TRUE;
|
fnCanException = `TRUE;
|
`R2:
|
`R2:
|
case(isn[`INSTRUCTION_S2])
|
case(isn[`INSTRUCTION_S2])
|
`ADD,`SUB,`MUL,`DIVMOD,`MULSU,`DIVMODSU: fnCanException = TRUE;
|
`ADD,`SUB,`MUL,
|
|
`DIV,`MULSU,`DIVSU,
|
|
`MOD,`MODSU:
|
|
fnCanException = TRUE;
|
`RTI: fnCanException = TRUE;
|
`RTI: fnCanException = TRUE;
|
default: fnCanException = FALSE;
|
default: fnCanException = FALSE;
|
endcase
|
endcase
|
`Bcc: fnCanException = TRUE;
|
`Bcc: fnCanException = TRUE;
|
`BEQI: fnCanException = TRUE;
|
`BEQI: fnCanException = TRUE;
|
| Line 247... |
Line 258... |
`LCX: IsLoad = TRUE;
|
`LCX: IsLoad = TRUE;
|
`LCUX: IsLoad = TRUE;
|
`LCUX: IsLoad = TRUE;
|
`LHX: IsLoad = TRUE;
|
`LHX: IsLoad = TRUE;
|
`LHUX: IsLoad = TRUE;
|
`LHUX: IsLoad = TRUE;
|
`LWX: IsLoad = TRUE;
|
`LWX: IsLoad = TRUE;
|
|
`LVBX: IsLoad = TRUE;
|
|
`LVBUX: IsLoad = TRUE;
|
|
`LVCX: IsLoad = TRUE;
|
|
`LVCUX: IsLoad = TRUE;
|
|
`LVHX: IsLoad = TRUE;
|
|
`LVHUX: IsLoad = TRUE;
|
|
`LVWX: IsLoad = TRUE;
|
`LWRX: IsLoad = TRUE;
|
`LWRX: IsLoad = TRUE;
|
`LVX: IsLoad = TRUE;
|
`LVX: IsLoad = TRUE;
|
`LVx: IsLoad = TRUE;
|
|
default: IsLoad = FALSE;
|
default: IsLoad = FALSE;
|
endcase
|
endcase
|
else
|
else
|
IsLoad = FALSE;
|
IsLoad = FALSE;
|
`LB: IsLoad = TRUE;
|
`LB: IsLoad = TRUE;
|
| Line 265... |
Line 282... |
`LVx: IsLoad = TRUE;
|
`LVx: IsLoad = TRUE;
|
default: IsLoad = FALSE;
|
default: IsLoad = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
|
function IsVolatileLoad;
|
|
input [47:0] isn;
|
|
case(isn[`INSTRUCTION_OP])
|
|
`MEMNDX:
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
|
case(isn[`INSTRUCTION_S2])
|
|
`LWRX: IsVolatileLoad = TRUE;
|
|
`LVBX: IsVolatileLoad = TRUE;
|
|
`LVBUX: IsVolatileLoad = TRUE;
|
|
`LVCX: IsVolatileLoad = TRUE;
|
|
`LVCUX: IsVolatileLoad = TRUE;
|
|
`LVHX: IsVolatileLoad = TRUE;
|
|
`LVHUX: IsVolatileLoad = TRUE;
|
|
`LVWX: IsVolatileLoad = TRUE;
|
|
default: IsVolatileLoad = FALSE;
|
|
endcase
|
|
else
|
|
IsVolatileLoad = FALSE;
|
|
`LWR: IsVolatileLoad = TRUE;
|
|
`LVx: IsVolatileLoad = TRUE;
|
|
default: IsVolatileLoad = FALSE;
|
|
endcase
|
|
endfunction
|
|
|
|
function IsStore;
|
|
input [47:0] isn;
|
|
case(isn[`INSTRUCTION_OP])
|
|
`MEMNDX:
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
|
case(isn[`INSTRUCTION_S2])
|
|
`SBX: IsStore = TRUE;
|
|
`SCX: IsStore = TRUE;
|
|
`SHX: IsStore = TRUE;
|
|
`SWX: IsStore = TRUE;
|
|
`SWCX: IsStore = TRUE;
|
|
`SVX: IsStore = TRUE;
|
|
`CASX: IsStore = TRUE;
|
|
`INC: IsStore = TRUE;
|
|
default: IsStore = FALSE;
|
|
endcase
|
|
else
|
|
IsStore = FALSE;
|
|
`SB: IsStore = TRUE;
|
|
`Sx: IsStore = TRUE;
|
|
`SWC: IsStore = TRUE;
|
|
`INC: IsStore = TRUE;
|
|
`SV: IsStore = TRUE;
|
|
`CAS: IsStore = TRUE;
|
|
`AMO: IsStore = TRUE;
|
|
default: IsStore = FALSE;
|
|
endcase
|
|
endfunction
|
|
|
function [0:0] IsMem;
|
function [0:0] IsMem;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`MEMNDX: IsMem = TRUE;
|
`MEMNDX: IsMem = TRUE;
|
`AMO: IsMem = TRUE;
|
`AMO: IsMem = TRUE;
|
| Line 294... |
Line 364... |
`MEMNDX: IsMemNdx = TRUE;
|
`MEMNDX: IsMemNdx = TRUE;
|
default: IsMemNdx = FALSE;
|
default: IsMemNdx = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
|
function [2:0] MemSize;
|
|
input [47:0] isn;
|
|
case(isn[`INSTRUCTION_OP])
|
|
`MEMNDX:
|
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
|
case(isn[`INSTRUCTION_S2])
|
|
`LVBX,`LVBUX: MemSize = byt;
|
|
`LBX,`LBUX,`SBX: MemSize = byt;
|
|
`LVCX,`LVCUX: MemSize = wyde;
|
|
`LCX,`LCUX,`SCX: MemSize = wyde;
|
|
`LVHX,`LVHUX: MemSize = tetra;
|
|
`LHX,`SHX: MemSize = tetra;
|
|
`LHUX: MemSize = tetra;
|
|
`LVWX: MemSize = octa;
|
|
`LWX,`SWX: MemSize = octa;
|
|
`LWRX,`SWCX: MemSize = octa;
|
|
`LVX,`SVX: MemSize = octa;
|
|
`LVx:
|
|
case(isn[25:23])
|
|
3'd0,3'd1: MemSize = byt;
|
|
3'd2,3'd3: MemSize = wyde;
|
|
3'd4,3'd5: MemSize = tetra;
|
|
default: MemSize = octa;
|
|
endcase
|
|
default: MemSize = octa;
|
|
endcase
|
|
else
|
|
MemSize = octa;
|
|
`LB,`LBU,`SB: MemSize = byt;
|
|
`Lx,`LxU,`Sx,`LVx:
|
|
casez(isn[20:18])
|
|
3'b100: MemSize = octa;
|
|
3'b?10: MemSize = tetra;
|
|
3'b??1: MemSize = wyde;
|
|
default: MemSize = octa;
|
|
endcase
|
|
`LWR,`SWC: MemSize = octa;
|
|
`LV,`SV: MemSize = octa;
|
|
`AMO:
|
|
case(isn[23:21])
|
|
3'd0: MemSize = byt;
|
|
3'd1: MemSize = wyde;
|
|
3'd2: MemSize = tetra;
|
|
3'd3: MemSize = octa;
|
|
default: MemSize = octa;
|
|
endcase
|
|
default: MemSize = octa;
|
|
endcase
|
|
endfunction
|
|
|
function IsCAS;
|
function IsCAS;
|
input [47:0] isn;
|
input [47:0] isn;
|
case(isn[`INSTRUCTION_OP])
|
case(isn[`INSTRUCTION_OP])
|
`MEMNDX:
|
`MEMNDX:
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
if (isn[`INSTRUCTION_L2]==2'b00)
|
| Line 470... |
Line 590... |
`LVx: HasConst = TRUE;
|
`LVx: HasConst = TRUE;
|
default: HasConst = FALSE;
|
default: HasConst = FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
|
function IsOddball;
|
|
input [47:0] instr;
|
|
//if (|iqentry_exc[head])
|
|
// IsOddball = TRUE;
|
|
//else
|
|
case(instr[`INSTRUCTION_OP])
|
|
`BRK: IsOddball = TRUE;
|
|
`IVECTOR:
|
|
case(instr[`INSTRUCTION_S2])
|
|
`VSxx: IsOddball = TRUE;
|
|
default: IsOddball = FALSE;
|
|
endcase
|
|
`RR:
|
|
case(instr[`INSTRUCTION_S2])
|
|
`VMOV: IsOddball = TRUE;
|
|
`SEI,`RTI: IsOddball = TRUE;
|
|
default: IsOddball = FALSE;
|
|
endcase
|
|
`MEMNDX:
|
|
case(instr[`INSTRUCTION_S2])
|
|
`CACHEX: IsOddball = TRUE;
|
|
default: IsOddball = FALSE;
|
|
endcase
|
|
`CSRRW,`REX,`CACHE,`FLOAT: IsOddball = TRUE;
|
|
default: IsOddball = FALSE;
|
|
endcase
|
|
endfunction
|
|
|
function IsRFW;
|
function IsRFW;
|
input [47:0] isn;
|
input [47:0] isn;
|
casez(isn[`INSTRUCTION_OP])
|
casez(isn[`INSTRUCTION_OP])
|
`IVECTOR: IsRFW = TRUE;
|
`IVECTOR: IsRFW = TRUE;
|
`FVECTOR: IsRFW = TRUE;
|
`FVECTOR: IsRFW = TRUE;
|
| Line 491... |
Line 639... |
`OR: IsRFW = TRUE;
|
`OR: IsRFW = TRUE;
|
`XOR: IsRFW = TRUE;
|
`XOR: IsRFW = TRUE;
|
`MULU: IsRFW = TRUE;
|
`MULU: IsRFW = TRUE;
|
`MULSU: IsRFW = TRUE;
|
`MULSU: IsRFW = TRUE;
|
`MUL: IsRFW = TRUE;
|
`MUL: IsRFW = TRUE;
|
`DIVMODU: IsRFW = TRUE;
|
`MULUH: IsRFW = TRUE;
|
`DIVMODSU: IsRFW = TRUE;
|
`MULSUH: IsRFW = TRUE;
|
`DIVMOD:IsRFW = TRUE;
|
`MULH: IsRFW = TRUE;
|
|
`DIVU: IsRFW = TRUE;
|
|
`DIVSU: IsRFW = TRUE;
|
|
`DIV:IsRFW = TRUE;
|
|
`MODU: IsRFW = TRUE;
|
|
`MODSU: IsRFW = TRUE;
|
|
`MOD:IsRFW = TRUE;
|
`MOV: IsRFW = TRUE;
|
`MOV: IsRFW = TRUE;
|
`VMOV: IsRFW = TRUE;
|
`VMOV: IsRFW = TRUE;
|
`SHIFTR,`SHIFT31,`SHIFT63:
|
`SHIFTR,`SHIFT31,`SHIFT63:
|
IsRFW = TRUE;
|
IsRFW = TRUE;
|
`MIN,`MAX: IsRFW = TRUE;
|
`MIN,`MAX: IsRFW = TRUE;
|
| Line 514... |
Line 668... |
`LCX: IsRFW = TRUE;
|
`LCX: IsRFW = TRUE;
|
`LCUX: IsRFW = TRUE;
|
`LCUX: IsRFW = TRUE;
|
`LHX: IsRFW = TRUE;
|
`LHX: IsRFW = TRUE;
|
`LHUX: IsRFW = TRUE;
|
`LHUX: IsRFW = TRUE;
|
`LWX: IsRFW = TRUE;
|
`LWX: IsRFW = TRUE;
|
|
`LVBX: IsRFW = TRUE;
|
|
`LVBUX: IsRFW = TRUE;
|
|
`LVCX: IsRFW = TRUE;
|
|
`LVCUX: IsRFW = TRUE;
|
|
`LVHX: IsRFW = TRUE;
|
|
`LVHUX: IsRFW = TRUE;
|
|
`LVWX: IsRFW = TRUE;
|
|
`LWX: IsRFW = TRUE;
|
`LWRX: IsRFW = TRUE;
|
`LWRX: IsRFW = TRUE;
|
`LVX: IsRFW = TRUE;
|
`LVX: IsRFW = TRUE;
|
`LVx: IsRFW = TRUE;
|
|
`CASX: IsRFW = TRUE;
|
`CASX: IsRFW = TRUE;
|
default: IsRFW = FALSE;
|
default: IsRFW = FALSE;
|
endcase
|
endcase
|
else
|
else
|
IsRFW = FALSE;
|
IsRFW = FALSE;
|
| Line 582... |
Line 743... |
`SHIFT63: fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
|
`SHIFT63: fnWe = (~isn[25] & isn[21]) ? 8'hFF : 8'hFF;
|
`SLT,`SLTU,`SLE,`SLEU,
|
`SLT,`SLTU,`SLE,`SLEU,
|
`ADD,`SUB,
|
`ADD,`SUB,
|
`AND,`OR,`XOR,
|
`AND,`OR,`XOR,
|
`NAND,`NOR,`XNOR,
|
`NAND,`NOR,`XNOR,
|
`DIVMOD,`DIVMODU,`DIVMODSU,
|
`DIV,`DIVU,`DIVSU,
|
`MUL,`MULU,`MULSU:
|
`MOD,`MODU,`MODSU,
|
|
`MUL,`MULU,`MULSU,
|
|
`MULH,`MULUH,`MULSUH:
|
case(isn[25:23])
|
case(isn[25:23])
|
3'b000: fnWe = 8'h01;
|
3'b000: fnWe = 8'h01;
|
3'b001: fnWe = 8'h03;
|
3'b001: fnWe = 8'h03;
|
3'b010: fnWe = 8'h0F;
|
3'b010: fnWe = 8'h0F;
|
3'b011: fnWe = 8'hFF;
|
3'b011: fnWe = 8'hFF;
|
| Line 760... |
Line 923... |
endcase
|
endcase
|
// bus[`IB_RT] <= fnRt(instr,ven,vl,thrd) | {thrd,7'b0};
|
// bus[`IB_RT] <= fnRt(instr,ven,vl,thrd) | {thrd,7'b0};
|
// bus[`IB_RC] <= fnRc(instr,ven,thrd) | {thrd,7'b0};
|
// bus[`IB_RC] <= fnRc(instr,ven,thrd) | {thrd,7'b0};
|
// bus[`IB_RA] <= fnRa(instr,ven,vl,thrd) | {thrd,7'b0};
|
// bus[`IB_RA] <= fnRa(instr,ven,vl,thrd) | {thrd,7'b0};
|
bus[`IB_IMM] <= HasConst(instr);
|
bus[`IB_IMM] <= HasConst(instr);
|
bus[`IB_A3V] <= Source3Valid(instr);
|
// bus[`IB_A3V] <= Source3Valid(instr);
|
bus[`IB_A2V] <= Source2Valid(instr);
|
// bus[`IB_A2V] <= Source2Valid(instr);
|
bus[`IB_A1V] <= Source1Valid(instr);
|
// bus[`IB_A1V] <= Source1Valid(instr);
|
bus[`IB_BT] <= (IsBranch(instr) && predict_taken);
|
bus[`IB_BT] <= (IsBranch(instr) && predict_taken);
|
bus[`IB_ALU] <= IsALU;
|
bus[`IB_ALU] <= IsALU;
|
bus[`IB_ALU0] <= IsAlu0Only(instr);
|
bus[`IB_ALU0] <= IsAlu0Only(instr);
|
bus[`IB_FPU] <= IsFPU(instr);
|
bus[`IB_FPU] <= IsFPU(instr);
|
bus[`IB_FC] <= IsFlowCtrl;
|
bus[`IB_FC] <= IsFlowCtrl;
|
bus[`IB_CANEX] <= fnCanException(instr);
|
bus[`IB_CANEX] <= fnCanException(instr);
|
|
bus[`IB_LOADV] <= IsVolatileLoad(instr);
|
bus[`IB_LOAD] <= IsLoad(instr);
|
bus[`IB_LOAD] <= IsLoad(instr);
|
bus[`IB_PRELOAD] <= IsLoad(instr) && Rt==5'd0;
|
bus[`IB_PRELOAD] <= IsLoad(instr) && Rt==5'd0;
|
|
bus[`IB_STORE] <= IsStore(instr);
|
|
bus[`IB_ODDBALL] <= IsOddball(instr);
|
|
bus[`IB_MEMSZ] <= MemSize(instr);
|
bus[`IB_MEM] <= IsMem(instr);
|
bus[`IB_MEM] <= IsMem(instr);
|
bus[`IB_MEMNDX] <= IsMemNdx(instr);
|
bus[`IB_MEMNDX] <= IsMemNdx(instr);
|
bus[`IB_RMW] <= IsCAS(instr) || IsAMO(instr) || IsInc(instr);
|
bus[`IB_RMW] <= IsCAS(instr) || IsAMO(instr) || IsInc(instr);
|
bus[`IB_MEMDB] <= IsMemdb(instr);
|
bus[`IB_MEMDB] <= IsMemdb(instr);
|
bus[`IB_MEMSB] <= IsMemsb(instr);
|
bus[`IB_MEMSB] <= IsMemsb(instr);
|
| Line 800... |
Line 967... |
parameter TRUE = 1'b1;
|
parameter TRUE = 1'b1;
|
parameter FALSE = 1'b0;
|
parameter FALSE = 1'b0;
|
|
|
always @*
|
always @*
|
casez(instr[`INSTRUCTION_OP])
|
casez(instr[`INSTRUCTION_OP])
|
`R2: if (instr[`INSTRUCTION_L2]==2'b00)
|
`R2:
|
|
if (instr[`INSTRUCTION_L2]==2'b00)
|
case(instr[`INSTRUCTION_S2])
|
case(instr[`INSTRUCTION_S2])
|
`VMOV: IsALU = TRUE;
|
`VMOV: IsALU = TRUE;
|
`RTI: IsALU = FALSE;
|
`RTI: IsALU = FALSE;
|
default: IsALU = TRUE;
|
default: IsALU = TRUE;
|
endcase
|
endcase
|
