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https://opencores.org/ocsvn/thor/thor/trunk
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| Rev 50 |
Rev 51 |
| Line 109... |
Line 109... |
wire sptr_o;
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wire sptr_o;
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wire cs_pit = adr[31:8]==24'hFFDC11;
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wire cs_pit = adr[31:8]==24'hFFDC11;
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wire cs_crd = adr[31:11]==21'd0; // $00000000 in virtual address space
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wire cs_crd = adr[31:11]==21'd0; // $00000000 in virtual address space
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// Need to recreate the a2 address bit for 32 bit peripherals.
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wire [31:0] adr32 = {adr[31:3],|sel_o[7:4],2'b00};
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wire [31:0] dat32 = |sel_o[7:4] ? dat_o[63:32] : dat_o[31:0];
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FT64_pit upit1
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FT64_pit upit1
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(
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(
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.rst_i(rst_i),
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.rst_i(rst_i),
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.clk_i(clk_i),
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.clk_i(clk_i),
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.cs_i(cs_pit),
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.cs_i(cs_pit),
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.cyc_i(cyc),
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.cyc_i(cyc),
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.stb_i(stb),
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.stb_i(stb),
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.ack_o(pit_ack),
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.ack_o(pit_ack),
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.sel_i(sel_o[7:4]|sel_o[3:0]),
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.sel_i(sel_o[7:4]|sel_o[3:0]),
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.we_i(we_o),
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.we_i(we_o),
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.adr_i(adr[5:0]),
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.adr_i(adr32[5:0]),
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.dat_i(dat_o[31:0]),
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.dat_i(dat32),
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.dat_o(pit_dato),
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.dat_o(pit_dato),
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.clk0(1'b0),
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.clk0(1'b0),
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.gate0(1'b0),
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.gate0(1'b0),
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.out0(pit_out0),
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.out0(pit_out0),
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.clk1(1'b0),
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.clk1(1'b0),
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| Line 141... |
Line 145... |
.clk_i(clk_i), // system clock
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.clk_i(clk_i), // system clock
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.cyc_i(cyc),
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.cyc_i(cyc),
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.stb_i(stb),
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.stb_i(stb),
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.ack_o(pic_ack), // controller is ready
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.ack_o(pic_ack), // controller is ready
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.wr_i(we_o), // write
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.wr_i(we_o), // write
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.adr_i(adr), // address
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.adr_i(adr32), // address
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.dat_i(dat_o[31:0]),
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.dat_i(dat32),
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.dat_o(pic_dato),
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.dat_o(pic_dato),
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.vol_o(), // volatile register selected
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.vol_o(), // volatile register selected
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.i1(i1),
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.i1(i1),
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.i2(i2),
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.i2(i2),
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.i3(i3),
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.i3(i3),
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| Line 197... |
Line 201... |
.s_ex_i(icl),
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.s_ex_i(icl),
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.s_cyc_i(cyc),
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.s_cyc_i(cyc),
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.s_stb_i(stb),
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.s_stb_i(stb),
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.s_ack_o(mmu_ack),
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.s_ack_o(mmu_ack),
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.s_wr_i(we_o),
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.s_wr_i(we_o),
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.s_adr_i(adr),
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.s_adr_i(adr32),
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.s_dat_i(dat_o[31:0]),
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.s_dat_i(dat32),
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.s_dat_o(mmu_dato),
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.s_dat_o(mmu_dato),
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.cyc_o(cyc_o),
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.cyc_o(cyc_o),
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.stb_o(stb_o),
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.stb_o(stb_o),
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.pea_o(adr_o),
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.pea_o(adr_o),
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.exv_o(exv),
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.exv_o(exv),
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| Line 231... |
Line 235... |
4'b001?: dati <= {2{pit_dato}};
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4'b001?: dati <= {2{pit_dato}};
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4'b0001: dati <= crd_dato;
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4'b0001: dati <= crd_dato;
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default: dati <= dat_i;
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default: dati <= dat_i;
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endcase
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endcase
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assign ack = ack_i|mmu_ack|pic_ack|crd_ack;
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assign ack = ack_i|mmu_ack|pic_ack|pit_ack|crd_ack;
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FT64 ucpu1
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FT64 ucpu1
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(
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(
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.hartid(hartid_i),
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.hartid(hartid_i),
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.rst(rst_i),
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.rst(rst_i),
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