| Line 55... |
Line 55... |
// This register resets the edge sense circuitry
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// This register resets the edge sense circuitry
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// indicated by the low order five bits of the input data.
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// indicated by the low order five bits of the input data.
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//
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//
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// 0x80 - irq control for irq #0
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// 0x80 - irq control for irq #0
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// 0x84 - irq control for irq #1
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// 0x84 - irq control for irq #1
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// bits 0 to 6 = cause code to issue
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// bits 0 to 7 = cause code to issue
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// bits 8 to 10 = irq level to issue
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// bits 8 to 11 = irq level to issue
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// bit 16 = irq enable
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// bit 16 = irq enable
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// bit 17 = edge sensitivity
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// bit 17 = edge sensitivity
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//=============================================================================
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//=============================================================================
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module FT64_pic
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module FT64_pic
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| Line 95... |
Line 95... |
reg [31:0] iedge;
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reg [31:0] iedge;
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reg [31:0] rste;
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reg [31:0] rste;
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reg [31:0] es;
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reg [31:0] es;
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reg [5:0] cause_base;
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reg [5:0] cause_base;
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reg [3:0] irq [0:31];
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reg [3:0] irq [0:31];
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reg [6:0] cause [0:31];
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reg [7:0] cause [0:31];
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integer n;
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integer n;
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initial begin
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initial begin
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ie <= 32'h0;
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ie <= 32'h0;
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es <= 32'hFFFFFFFF;
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es <= 32'hFFFFFFFF;
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rste <= 32'h0;
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rste <= 32'h0;
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for (n = 0; n < 32; n = n + 1) begin
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for (n = 0; n < 32; n = n + 1) begin
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cause[n] <= 7'h00;
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cause[n] <= 8'h00;
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irq[n] <= 4'h8;
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irq[n] <= 4'h8;
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end
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end
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end
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end
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wire cs = cyc_i && stb_i && adr_i[31:8]==pIOAddress[31:8];
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wire cs = cyc_i && stb_i && adr_i[31:8]==pIOAddress[31:8];
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| Line 136... |
Line 136... |
ie[dat_i[4:0]] <= adr_i[2];
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ie[dat_i[4:0]] <= adr_i[2];
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6'd4: es <= dat_i[31:0];
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6'd4: es <= dat_i[31:0];
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6'd5: rste[dat_i[4:0]] <= 1'b1;
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6'd5: rste[dat_i[4:0]] <= 1'b1;
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6'b1?????:
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6'b1?????:
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begin
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begin
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cause[adr_i[6:2]] <= dat_i[6:0];
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cause[adr_i[6:2]] <= dat_i[7:0];
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irq[adr_i[6:2]] <= dat_i[11:8];
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irq[adr_i[6:2]] <= dat_i[11:8];
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ie[adr_i[6:2]] <= dat_i[16];
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ie[adr_i[6:2]] <= dat_i[16];
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es[adr_i[6:2]] <= dat_i[17];
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es[adr_i[6:2]] <= dat_i[17];
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end
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end
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endcase
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endcase
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| Line 153... |
Line 153... |
if (irqenc!=5'd0)
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if (irqenc!=5'd0)
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$display("PIC: %d",irqenc);
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$display("PIC: %d",irqenc);
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if (cs)
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if (cs)
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casez (adr_i[7:2])
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casez (adr_i[7:2])
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6'd0: dat_o <= {cause_base,3'd0} + irqenc;
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6'd0: dat_o <= {cause_base,3'd0} + irqenc;
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6'b1?????: dat_o <= {es[adr_i[6:2]],ie[adr_i[6:2]],4'b0,irq[adr_i[6:2]],1'b0,cause[adr_i[6:2]]};
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6'b1?????: dat_o <= {es[adr_i[6:2]],ie[adr_i[6:2]],4'b0,irq[adr_i[6:2]],cause[adr_i[6:2]]};
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default: dat_o <= ie;
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default: dat_o <= ie;
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endcase
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endcase
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else
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else
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dat_o <= 32'h0000;
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dat_o <= 32'h0000;
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end
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end
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assign irqo = (irqenc == 5'h0) ? 4'd0 : irq[irqenc];
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assign irqo = (irqenc == 5'h0) ? 4'd0 : irq[irqenc];
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assign causeo = (irqenc == 5'h0) ? 7'd0 : cause[irqenc];
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assign causeo = (irqenc == 5'h0) ? 8'd0 : cause[irqenc];
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assign nmio = nmii & ie[0];
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assign nmio = nmii & ie[0];
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// Edge detect circuit
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// Edge detect circuit
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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