Line 77... |
Line 77... |
output vol_o, // volatile register selected
|
output vol_o, // volatile register selected
|
input i1, i2, i3, i4, i5, i6, i7,
|
input i1, i2, i3, i4, i5, i6, i7,
|
i8, i9, i10, i11, i12, i13, i14, i15,
|
i8, i9, i10, i11, i12, i13, i14, i15,
|
i16, i17, i18, i19, i20, i21, i22, i23,
|
i16, i17, i18, i19, i20, i21, i22, i23,
|
i24, i25, i26, i27, i28, i29, i30, i31,
|
i24, i25, i26, i27, i28, i29, i30, i31,
|
output [2:0] irqo, // normally connected to the processor irq
|
output [3:0] irqo, // normally connected to the processor irq
|
input nmii, // nmi input connected to nmi requester
|
input nmii, // nmi input connected to nmi requester
|
output nmio, // normally connected to the nmi of cpu
|
output nmio, // normally connected to the nmi of cpu
|
output [6:0] causeo
|
output [6:0] causeo
|
);
|
);
|
parameter pIOAddress = 32'hFFDC_0F00;
|
parameter pIOAddress = 32'hFFDC_0F00;
|
Line 94... |
Line 94... |
reg [31:0] ib;
|
reg [31:0] ib;
|
reg [31:0] iedge;
|
reg [31:0] iedge;
|
reg [31:0] rste;
|
reg [31:0] rste;
|
reg [31:0] es;
|
reg [31:0] es;
|
reg [5:0] cause_base;
|
reg [5:0] cause_base;
|
reg [2:0] irq [0:31];
|
reg [3:0] irq [0:31];
|
reg [6:0] cause [0:31];
|
reg [6:0] cause [0:31];
|
|
|
wire cs = cyc_i && stb_i && adr_i[31:8]==pIOAddress[31:8];
|
wire cs = cyc_i && stb_i && adr_i[31:8]==pIOAddress[31:8];
|
assign vol_o = cs;
|
assign vol_o = cs;
|
|
|
Line 126... |
Line 126... |
6'd4: es <= dat_i[31:0];
|
6'd4: es <= dat_i[31:0];
|
6'd5: rste[dat_i[4:0]] <= 1'b1;
|
6'd5: rste[dat_i[4:0]] <= 1'b1;
|
6'b1xxxxx:
|
6'b1xxxxx:
|
begin
|
begin
|
cause[adr_i[6:2]] <= dat_i[6:0];
|
cause[adr_i[6:2]] <= dat_i[6:0];
|
irq[adr_i[6:2]] <= dat_i[10:8];
|
irq[adr_i[6:2]] <= dat_i[11:8];
|
ie[adr_i[6:2]] <= dat_i[16];
|
ie[adr_i[6:2]] <= dat_i[16];
|
es[adr_i[6:2]] <= dat_i[17];
|
es[adr_i[6:2]] <= dat_i[17];
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
Line 142... |
Line 142... |
if (irqenc!=5'd0)
|
if (irqenc!=5'd0)
|
$display("PIC: %d",irqenc);
|
$display("PIC: %d",irqenc);
|
if (cs)
|
if (cs)
|
casex (adr_i[7:2])
|
casex (adr_i[7:2])
|
6'd0: dat_o <= {cause_base,3'd0} + irqenc;
|
6'd0: dat_o <= {cause_base,3'd0} + irqenc;
|
6'b1xxxxx: dat_o <= {es[adr_i[6:2]],ie[adr_i[6:2]],5'b0,irq[adr_i[6:2]],1'b0,cause[adr_i[6:2]]};
|
6'b1xxxxx: dat_o <= {es[adr_i[6:2]],ie[adr_i[6:2]],4'b0,irq[adr_i[6:2]],1'b0,cause[adr_i[6:2]]};
|
default: dat_o <= ie;
|
default: dat_o <= ie;
|
endcase
|
endcase
|
else
|
else
|
dat_o <= 32'h0000;
|
dat_o <= 32'h0000;
|
end
|
end
|
|
|
assign irqo = (irqenc == 5'h0) ? 3'd0 : irq[irqenc];
|
assign irqo = (irqenc == 5'h0) ? 4'd0 : irq[irqenc];
|
assign causeo = (irqenc == 5'h0) ? 7'd0 : cause[irqenc];
|
assign causeo = (irqenc == 5'h0) ? 7'd0 : cause[irqenc];
|
assign nmio = nmii & ie[0];
|
assign nmio = nmii & ie[0];
|
|
|
// Edge detect circuit
|
// Edge detect circuit
|
integer n;
|
integer n;
|