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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [twoway/] [FT64_regfile2w6r_oc.v] - Diff between revs 49 and 50

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Rev 49	Rev 50
Line 28...	Line 28...
`module FT64_regfileRam_sim(clka, ena, wea, addra, dina, clkb, enb, addrb, doutb);`	`module FT64_regfileRam_sim(clka, ena, wea, addra, dina, clkb, enb, addrb, doutb);`
`parameter WID=64;`	`parameter WID=64;`
`parameter RBIT = 11;`	`parameter RBIT = 11;`
`input clka;`	`input clka;`
`input ena;`	`input ena;`
`input [8:0] wea;`	`input [7:0] wea;`
`input [RBIT:0] addra;`	`input [RBIT:0] addra;`
`input [WID-1:0] dina;`	`input [WID-1:0] dina;`
`input clkb;`	`input clkb;`
`input enb;`	`input enb;`
`input [RBIT:0] addrb;`	`input [RBIT:0] addrb;`
Line 54...	Line 54...
`always @(posedge clka) if (ena & wea[3]) mem[addra][31:24] <= dina[31:24];`	`always @(posedge clka) if (ena & wea[3]) mem[addra][31:24] <= dina[31:24];`
`always @(posedge clka) if (ena & wea[4]) mem[addra][39:32] <= dina[39:32];`	`always @(posedge clka) if (ena & wea[4]) mem[addra][39:32] <= dina[39:32];`
`always @(posedge clka) if (ena & wea[5]) mem[addra][47:40] <= dina[47:40];`	`always @(posedge clka) if (ena & wea[5]) mem[addra][47:40] <= dina[47:40];`
`always @(posedge clka) if (ena & wea[6]) mem[addra][55:48] <= dina[55:48];`	`always @(posedge clka) if (ena & wea[6]) mem[addra][55:48] <= dina[55:48];`
`always @(posedge clka) if (ena & wea[7]) mem[addra][63:56] <= dina[63:56];`	`always @(posedge clka) if (ena & wea[7]) mem[addra][63:56] <= dina[63:56];`
`always @(posedge clka) if (ena & wea[8]) mem[addra][64] <= dina[64];`

`always @(posedge clkb)`	`always @(posedge clkb)`
`raddrb <= addrb;`	`raddrb <= addrb;`
`assign doutb = mem[raddrb];`	`assign doutb = mem[raddrb];`

Line 71...	Line 70...
`parameter RBIT = 11;`	`parameter RBIT = 11;`
`input clk4x;`	`input clk4x;`
`input clk;`	`input clk;`
`input wr0;`	`input wr0;`
`input wr1;`	`input wr1;`
`input [8:0] we0;`	`input [7:0] we0;`
`input [8:0] we1;`	`input [7:0] we1;`
`input [RBIT:0] wa0;`	`input [RBIT:0] wa0;`
`input [RBIT:0] wa1;`	`input [RBIT:0] wa1;`
`input [WID-1:0] i0;`	`input [WID-1:0] i0;`
`input [WID-1:0] i1;`	`input [WID-1:0] i1;`
`input rclk;`	`input rclk;`
Line 184...	Line 183...
`.wea(we),`	`.wea(we),`
`.addra(wa),`	`.addra(wa),`
`.dina(i),`	`.dina(i),`
`.clkb(rclk),`	`.clkb(rclk),`
`.enb(1'b1),`	`.enb(1'b1),`
	`.web(1'b0),`
`.addrb(ra0),`	`.addrb(ra0),`
	`.dinb(8'h00),`
`.doutb(o00)`	`.doutb(o00)`
`);`	`);`

`FT64_regfileRam urf11 (`	`FT64_regfileRam urf11 (`
`.clka(clk4x),`	`.clka(clk4x),`
Line 196...	Line 197...
`.wea(we),`	`.wea(we),`
`.addra(wa),`	`.addra(wa),`
`.dina(i),`	`.dina(i),`
`.clkb(rclk),`	`.clkb(rclk),`
`.enb(1'b1),`	`.enb(1'b1),`
	`.web(1'b0),`
`.addrb(ra1),`	`.addrb(ra1),`
	`.dinb(8'h00),`
`.doutb(o01)`	`.doutb(o01)`
`);`	`);`

`FT64_regfileRam urf12 (`	`FT64_regfileRam urf12 (`
`.clka(clk4x),`	`.clka(clk4x),`
Line 208...	Line 211...
`.wea(we),`	`.wea(we),`
`.addra(wa),`	`.addra(wa),`
`.dina(i),`	`.dina(i),`
`.clkb(rclk),`	`.clkb(rclk),`
`.enb(1'b1),`	`.enb(1'b1),`
	`.web(1'b0),`
`.addrb(ra2),`	`.addrb(ra2),`
	`.dinb(8'h00),`
`.doutb(o02)`	`.doutb(o02)`
`);`	`);`

`FT64_regfileRam urf13 (`	`FT64_regfileRam urf13 (`
`.clka(clk4x),`	`.clka(clk4x),`
Line 220...	Line 225...
`.wea(we),`	`.wea(we),`
`.addra(wa),`	`.addra(wa),`
`.dina(i),`	`.dina(i),`
`.clkb(rclk),`	`.clkb(rclk),`
`.enb(1'b1),`	`.enb(1'b1),`
	`.web(1'b0),`
`.addrb(ra3),`	`.addrb(ra3),`
	`.dinb(8'h00),`
`.doutb(o03)`	`.doutb(o03)`
`);`	`);`

`FT64_regfileRam urf14 (`	`FT64_regfileRam urf14 (`
`.clka(clk4x),`	`.clka(clk4x),`
Line 232...	Line 239...
`.wea(we),`	`.wea(we),`
`.addra(wa),`	`.addra(wa),`
`.dina(i),`	`.dina(i),`
`.clkb(rclk),`	`.clkb(rclk),`
`.enb(1'b1),`	`.enb(1'b1),`
	`.web(1'b0),`
`.addrb(ra4),`	`.addrb(ra4),`
	`.dinb(8'h00),`
`.doutb(o04)`	`.doutb(o04)`
`);`	`);`

`FT64_regfileRam urf15 (`	`FT64_regfileRam urf15 (`
`.clka(clk4x),`	`.clka(clk4x),`
Line 244...	Line 253...
`.wea(we),`	`.wea(we),`
`.addra(wa),`	`.addra(wa),`
`.dina(i),`	`.dina(i),`
`.clkb(rclk),`	`.clkb(rclk),`
`.enb(1'b1),`	`.enb(1'b1),`
	`.web(1'b0),`
`.addrb(ra5),`	`.addrb(ra5),`
	`.dinb(8'h00),`
`.doutb(o05)`	`.doutb(o05)`
`);`	`);`
`endif	`endif

`// The same clock edge that would normally update the register file is the`	`// The same clock edge that would normally update the register file is the`

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[/] [thor/] [trunk/] [FT64v5/] [rtl/] [twoway/] [FT64_regfile2w6r_oc.v] - Diff between revs 49 and 50