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[/] [thor/] [trunk/] [FT64v7/] [rtl/] [common/] [FT64_ipt.v] - Diff between revs 61 and 66

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Rev 61	Rev 66
Line 25...	Line 25...
`//`	`//`
`ifndef TRUE	`ifndef TRUE
`define TRUE 1'b1	`define TRUE 1'b1
`define FALSE 1'b0	`define FALSE 1'b0
`endif	`endif
//`define BYPASS 1'b1	`define BYPASS 1'b1

`module FT64_ipt(rst, clk, pkeys_i, ol_i, bte_i, cti_i, cs_i, icl_i, cyc_i, stb_i, ack_o, we_i, sel_i, vadr_i, dat_i, dat_o,`	`module FT64_ipt(rst, clk, pkeys_i, ol_i, bte_i, cti_i, cs_i, icl_i, cyc_i, stb_i, ack_o, we_i, sel_i, vadr_i, dat_i, dat_o,`
`bte_o, cti_o, cyc_o, ack_i, we_o, sel_o, padr_o, exv_o, rdv_o, wrv_o, prv_o, page_fault);`	`bte_o, cti_o, cyc_o, ack_i, we_o, sel_o, padr_o, exv_o, rdv_o, wrv_o, prv_o, page_fault);`
`input rst;`	`input rst;`
`input clk;`	`input clk;`
Line 154...	Line 154...
`cti_o <= cti_i;`	`cti_o <= cti_i;`
`always @(posedge clk)`	`always @(posedge clk)`
`sel_o <= sel_i;`	`sel_o <= sel_i;`
`ifdef BYPASS	`ifdef BYPASS
`always @(posedge clk)`	`always @(posedge clk)`
	`pt_wr <= 1'b0;`
	`always @(posedge clk)`
	`pt_ad <= 16'h0;`
	`always @(posedge clk)`
	`pt_dati <= 42'h0;`
	`always @(posedge clk)`
`cyc_o <= cyc_i;`	`cyc_o <= cyc_i;`
`always @(posedge clk)`	`always @(posedge clk)`
`we_o <= we_i;`	`we_o <= we_i;`
`always @(posedge clk)`	`always @(posedge clk)`
`padr_o <= vadr_i[31:0];`	`padr_o <= vadr_i[31:0];`
Line 169...	Line 175...
`wrv_o <= 1'b0;`	`wrv_o <= 1'b0;`
`always @(posedge clk)`	`always @(posedge clk)`
`prv_o <= 1'b0;`	`prv_o <= 1'b0;`
`always @(posedge clk)`	`always @(posedge clk)`
`page_fault <= 1'b0;`	`page_fault <= 1'b0;`
	`always @(posedge clk)`
	`ack_o <= 1'b0;`
`else	`else
`always @(posedge clk)`	`always @(posedge clk)`
`if (rst) begin`	`if (rst) begin`
`cyc_o <= 1'b0;`	`cyc_o <= 1'b0;`
`padr_o <= 32'hFFFC0100;`	`padr_o <= 32'hFFFC0100;`
Line 426...	Line 434...
`goto(S_CMP4);`	`goto(S_CMP4);`
`end`	`end`

`// Wait a clock cycle for a page fault to register.`	`// Wait a clock cycle for a page fault to register.`
`S_WAIT1:`	`S_WAIT1:`
	`if (!ack_i)`
`goto(S_IDLE);`	`goto(S_IDLE);`

`S_ACK:`	`S_ACK:`
`if (ack_i) begin`	`if (ack_i) begin`
`if (cti_i==3'b000 \|\| cti_i==3'b111) begin`	`if (cti_i==3'b000 \|\| cti_i==3'b111) begin`

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[/] [thor/] [trunk/] [FT64v7/] [rtl/] [common/] [FT64_ipt.v] - Diff between revs 61 and 66