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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2018 Robert Finch, Waterloo
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// \\__/ o\ (C) 2018-2019 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// FT64_fetchbuf_x1.v
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// FT64_fetchbuf_x1.v
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Line 118... |
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function IsBranch;
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function IsBranch;
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input [47:0] isn;
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input [47:0] isn;
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casex(isn[`INSTRUCTION_OP])
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casex(isn[`INSTRUCTION_OP])
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`Bcc: IsBranch = TRUE;
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`Bcc: IsBranch = TRUE;
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`BLcc: IsBranch = TRUE;
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`BBc: IsBranch = TRUE;
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`BBc: IsBranch = TRUE;
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`BEQI: IsBranch = TRUE;
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`BEQI: IsBranch = TRUE;
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`BNEI: IsBranch = TRUE;
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`BCHK: IsBranch = TRUE;
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`BCHK: IsBranch = TRUE;
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default: IsBranch = FALSE;
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default: IsBranch = FALSE;
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endcase
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endcase
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endfunction
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endfunction
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Line 134... |
IsJAL = isn[`INSTRUCTION_OP]==`JAL;
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IsJAL = isn[`INSTRUCTION_OP]==`JAL;
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endfunction
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endfunction
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function IsJmp;
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function IsJmp;
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input [47:0] isn;
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input [47:0] isn;
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IsJmp = isn[`INSTRUCTION_OP]==`JMP;
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IsJmp = isn[`INSTRUCTION_OP]==`JMP && isn[7]==1'b0;
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endfunction
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endfunction
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function IsCall;
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function IsCall;
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input [47:0] isn;
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input [47:0] isn;
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IsCall = isn[`INSTRUCTION_OP]==`CALL;
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IsCall = isn[`INSTRUCTION_OP]==`CALL && isn[7]==1'b0;
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endfunction
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endfunction
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function IsRet;
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function IsRet;
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input [47:0] isn;
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input [47:0] isn;
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IsRet = isn[`INSTRUCTION_OP]==`RET;
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IsRet = isn[`INSTRUCTION_OP]==`RET;
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Line 157... |
function IsRTI;
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function IsRTI;
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input [47:0] isn;
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input [47:0] isn;
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IsRTI = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_S2]==`RTI;
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IsRTI = isn[`INSTRUCTION_OP]==`R2 && isn[`INSTRUCTION_S2]==`RTI;
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endfunction
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endfunction
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function IsExec;
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input [47:0] isn;
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if (isn[7:6]==2'b00)
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case(isn[`INSTRUCTION_OP])
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`R2:
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case(isn[`INSTRUCTION_S2])
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`R1:
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case(isn[22:18])
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`EXEC: IsExec = TRUE;
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default: IsExec = FALSE;
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endcase
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default: IsExec = FALSE;
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endcase
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default: IsExec = FALSE;
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endcase
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else
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IsExec = FALSE;
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endfunction
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function [2:0] fnInsLength;
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function [2:0] fnInsLength;
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input [47:0] ins;
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input [47:0] ins;
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`ifdef SUPPORT_DCI
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`ifdef SUPPORT_DCI
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if (ins[`INSTRUCTION_OP]==`CMPRSSD)
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if (ins[`INSTRUCTION_OP]==`CMPRSSD)
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fnInsLength = 3'd2 | pred_on;
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fnInsLength = 3'd2 | pred_on;
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Line 236... |
begin
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begin
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case(fetchbufA_instr[`INSTRUCTION_OP])
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case(fetchbufA_instr[`INSTRUCTION_OP])
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`RET: branch_pcA = retpc0;
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`RET: branch_pcA = retpc0;
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`JMP,`CALL:
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`JMP,`CALL:
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begin
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begin
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`ifdef JMP40
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branch_pcA[39:0] = fetchbufA_instr[6] ? {fetchbufA_instr[47:8]} : {fetchbufA_pc[39:24],fetchbufA_instr[31:8]};
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branch_pcA[39:0] = fetchbufA_instr[6] ? {fetchbufA_instr[47:8]} : {fetchbufA_pc[39:24],fetchbufA_instr[31:8]};
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`else
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branch_pcA[39:0] = {fetchbufA_pc[39:24],fetchbufA_instr[31:8]};
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`endif
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branch_pcA[63:40] = fetchbufA_pc[63:40];
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branch_pcA[63:40] = fetchbufA_pc[63:40];
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end
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end
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`R2: branch_pcA = btgtA; // RTI
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`R2: branch_pcA = btgtA; // RTI
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`BRK,`JAL: branch_pcA = btgtA;
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`BRK,`JAL: branch_pcA = btgtA;
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default:
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default:
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begin
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begin
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branch_pcA[31:8] = fetchbufA_pc[31:8] +
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branch_pcA[31:0] = fetchbufA_pc[31:0] +
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((fetchbufA_instr[7:6]==2'b01) ? {{5{fetchbufA_instr[47]}},fetchbufA_instr[47:29]} : {{21{fetchbufA_instr[31]}},fetchbufA_instr[31:29]});
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((fetchbufA_instr[7:6]==2'b01) ? {{4{fetchbufA_instr[47]}},fetchbufA_instr[47:23],fetchbufA_instr[17:16],1'b0} : {{20{fetchbufA_instr[31]}},fetchbufA_instr[31:23],fetchbufA_instr[17:16],1'b0});
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branch_pcA[7:0] = {fetchbufA_instr[28:23],fetchbufA_instr[17:16]};
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branch_pcA[63:32] = fetchbufA_pc[63:32];
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branch_pcA[63:32] = fetchbufA_pc[63:32];
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end
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end
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endcase
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endcase
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end
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end
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Line 260... |
begin
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begin
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case(fetchbufB_instr[`INSTRUCTION_OP])
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case(fetchbufB_instr[`INSTRUCTION_OP])
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`RET: branch_pcB = retpc0;
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`RET: branch_pcB = retpc0;
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`JMP,`CALL:
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`JMP,`CALL:
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begin
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begin
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`ifdef JMP40
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branch_pcB[39:0] = fetchbufB_instr[6] ? {fetchbufB_instr[47:8]} : {fetchbufB_pc[39:24],fetchbufB_instr[31:8]};
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branch_pcB[39:0] = fetchbufB_instr[6] ? {fetchbufB_instr[47:8]} : {fetchbufB_pc[39:24],fetchbufB_instr[31:8]};
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`else
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branch_pcB[39:0] = {fetchbufB_pc[39:24],fetchbufB_instr[31:8]};
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`endif
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branch_pcB[63:40] = fetchbufB_pc[63:40];
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branch_pcB[63:40] = fetchbufB_pc[63:40];
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end
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end
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`R2: branch_pcB = btgtB; // RTI
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`R2: branch_pcB = btgtB; // RTI
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`BRK,`JAL: branch_pcB = btgtB;
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`BRK,`JAL: branch_pcB = btgtB;
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default:
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default:
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begin
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begin
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branch_pcB[31:8] = fetchbufB_pc[31:8] +
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branch_pcB[31:0] = fetchbufB_pc[31:0] +
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((fetchbufB_instr[7:6]==2'b01) ? {{5{fetchbufB_instr[47]}},fetchbufB_instr[47:29]} : {{21{fetchbufB_instr[31]}},fetchbufB_instr[31:29]});
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((fetchbufB_instr[7:6]==2'b01) ? {{4{fetchbufB_instr[47]}},fetchbufB_instr[47:23],fetchbufB_instr[17:16],1'b0} : {{20{fetchbufB_instr[31]}},fetchbufB_instr[31:23],fetchbufB_instr[17:16],1'b0});
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branch_pcB[7:0] = {fetchbufB_instr[28:23],fetchbufB_instr[17:16]};
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branch_pcB[63:32] = fetchbufB_pc[63:32];
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branch_pcB[63:32] = fetchbufB_pc[63:32];
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end
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end
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endcase
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endcase
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end
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end
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| Line 468... |
Line 495... |
`ifdef SUPPORT_DCI
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`ifdef SUPPORT_DCI
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if (insn0[5:0]==`CMPRSSD)
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if (insn0[5:0]==`CMPRSSD)
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insln0 <= 3'd2 | pred_on;
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insln0 <= 3'd2 | pred_on;
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else
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else
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`endif
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`endif
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if (insn0[7:6]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC)
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if (IsExec(insn0))
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insln0 <= fnInsLength(codebuf0);
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insln0 <= fnInsLength(codebuf0); //???? should be 4?
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else
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else
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insln0 <= fnInsLength(insn0);
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insln0 <= fnInsLength(insn0);
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end
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end
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| Line 484... |
Line 511... |
cinsn0 <= expand0;
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cinsn0 <= expand0;
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else if (insn0[5:0]==`CMPRSSD && !pred_on)
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else if (insn0[5:0]==`CMPRSSD && !pred_on)
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cinsn0 <= expand0;
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cinsn0 <= expand0;
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else
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else
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`endif
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`endif
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if (insn0[7:6]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC && !pred_on)
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if (IsExec(insn0) && !pred_on)
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cinsn0 <= codebuf0;
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cinsn0 <= codebuf0;
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else if (insn0[15:14]==2'b00 && insn0[`INSTRUCTION_OP]==`EXEC && pred_on)
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else if (IsExec(insn0[55:8]) && pred_on)
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cinsn0 <= codebuf0;
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cinsn0 <= codebuf0;
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else if (insn0[15] & pred_on)
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else if (insn0[15] & pred_on)
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cinsn0 <= {xinsn0,insn0[7:0]};
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cinsn0 <= {xinsn0,insn0[7:0]};
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else if (insn0[7] & ~pred_on)
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else if (insn0[7] & ~pred_on)
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cinsn0 <= xinsn0;
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cinsn0 <= xinsn0;
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