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URL https://opencores.org/ocsvn/thor/thor/trunk

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[/] [thor/] [trunk/] [bench/] [Thor_tb.v] - Diff between revs 2 and 21

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Rev 2 Rev 21
Line 3... Line 3... 
parameter DBW=32;
 
parameter DBW=32;
 
reg rst;
 
reg rst;
 
reg clk;
 
reg clk;
 
reg nmi;
 
reg nmi;
 
reg p100Hz;
 
reg p100Hz;
 
 
 
reg p1000Hz;
 
wire [2:0] cti;
 
wire [2:0] cti;
 
wire cpu_clk;
 
wire cpu_clk;
 
wire cyc;
 
wire cyc;
 
wire stb;
 
wire stb;
 
wire we;
 
wire we;
 
wire [7:0] sel;
 
wire [7:0] sel;
 
wire br_ack;
 
wire br_ack;
 
wire [31:0] adr;
 
wire [31:0] adr;
 
wire [DBW-1:0] br_dato;
 
wire [DBW+6:0] br_dato;
 
wire scr_ack;
 
wire scr_ack;
 
wire [63:0] scr_dato;
 
wire [63:0] scr_dato;
 
 
 
reg [31:0] rammem [0:1048575];
 
 
 
wire err1,err2;
 
 
 
 
 
wire cpu_ack;
 
wire cpu_ack;
 
wire [DBW-1:0] cpu_dati;
 
wire [DBW-1:0] cpu_dati;
 
wire [DBW-1:0] cpu_dato;
 
wire [DBW-1:0] cpu_dato;
 
wire pic_ack,irq;
 
wire pic_ack,irq;
 
wire [31:0] pic_dato;
 
wire [31:0] pic_dato;
 
wire [7:0] vecno;
 
wire [7:0] vecno;
 
 
 
wire baud16;
 
 
 
wire uart_rxd;
 
 
 
wire uart_ack;
 
 
 
wire uart_irq;
 
 
 
wire [7:0] uart_dato;
 
wire LEDS_ack;
 
wire LEDS_ack;
 
 
 
 
 
initial begin
 
initial begin
 
        #0 rst = 1'b0;
 
        #0 rst = 1'b0;
 
        #0 clk = 1'b0;
 
        #0 clk = 1'b0;
 
        #0 nmi = 1'b0;
 
        #0 nmi = 1'b0;
 
        #0 p100Hz = 1'b0;
 
        #0 p100Hz = 1'b0;
 
 
 
        #0 p1000Hz = 1'b1;
 
        #10 rst = 1'b1;
 
        #10 rst = 1'b1;
 
        #50 rst = 1'b0;
 
        #50 rst = 1'b0;
 
        #19550 nmi = 1'b1;
 
        #20800 nmi = 1'b1;
 
        #20 nmi = 1'b0;
 
        #20 nmi = 1'b0;
 
end
 
end
 
 
 
 
 
always #5 clk = ~clk;
 
always #5 clk = ~clk;
 
always #10000 p100Hz = ~p100Hz;
 
always #10000 p100Hz = ~p100Hz;
 
 
 
always #3000 p1000Hz = ~p1000Hz;
 
 
 
 
 
 
 
wire ram_cs = cyc && stb && adr[31:28]==4'd0 && adr[31:14]!= 18'h0000;
 
 
 
wire [31:0] ramo = ram_cs ? rammem[adr[21:2]] : 32'd0;
 
 
 
always @(posedge clk)
 
 
 
    if (ram_cs & we) begin
 
 
 
        if (sel[0]) rammem[adr[21:2]][7:0] <= cpu_dato[7:0];
 
 
 
        if (sel[1]) rammem[adr[21:2]][15:8] <= cpu_dato[15:8];
 
 
 
        if (sel[2]) rammem[adr[21:2]][23:16] <= cpu_dato[23:16];
 
 
 
        if (sel[3]) rammem[adr[21:2]][31:24] <= cpu_dato[31:24];
 
 
 
    end
 
 
 
 
 
assign LEDS_ack = cyc && stb && adr[31:8]==32'hFFDC06;
 
assign LEDS_ack = cyc && stb && adr[31:8]==32'hFFDC06;
 
always @(posedge clk)
 
always @(posedge clk)
 
        if (LEDS_ack)
 
        if (LEDS_ack)
 
                $display("LEDS: %b", cpu_dato[7:0]);
 
                $display("LEDS: %b", cpu_dato[7:0]);
 
 
 
 
 
 
 
always @(posedge clk)
 
 
 
    if ((err1|err2)&&$time > 11000)
 
 
 
        $stop;
 
 
 
 
 
wire tc1_ack, tc2_ack;
 
wire tc1_ack, tc2_ack;
 
wire kbd_ack;
 
wire kbd_ack;
 
wire [31:0] tc1_dato, tc2_dato;
 
wire [31:0] tc1_dato, tc2_dato;
 
wire [7:0] kbd_dato;
 
wire [7:0] kbd_dato;
 
 
 
 
Line 55... Line 78... 
assign cpu_ack =
 
assign cpu_ack =
 
        LEDS_ack |
 
        LEDS_ack |
 
        scr_ack |
 
        scr_ack |
 
        br_ack |
 
        br_ack |
 
        tc1_ack | tc2_ack |
 
        tc1_ack | tc2_ack |
 
        kbd_ack | pic_ack
 
        kbd_ack | pic_ack |
 
 
 
        ram_cs | uart_ack
 
        ;
 
        ;
 
assign cpu_dati =
 
assign cpu_dati =
 
        scr_dato |
 
        scr_dato |
 
        br_dato |
 
        br_dato |
 
        tc1_dato | tc2_dato |
 
        tc1_dato | tc2_dato |
 
        {4{kbd_dato}} |
 
        {4{kbd_dato}} |
 
        pic_dato
 
        pic_dato |
 
 
 
        ramo |
 
 
 
        {4{uart_dato}}
 
        ;
 
        ;
 
 
 
 
 
 
 
rtfSerialTxSim ussim1
 
 
 
(
 
 
 
    .rst(rst),
 
 
 
    .baud16(baud16),
 
 
 
    .txd(uart_rxd)
 
 
 
);
 
 
 
 
 
 
 
rtfSimpleUart uuart1
 
 
 
(
 
 
 
        // WISHBONE Slave interface
 
 
 
        .rst_i(rst),                // reset
 
 
 
        .clk_i(clk),        // eg 100.7MHz
 
 
 
        .cyc_i(cyc),            // cycle valid
 
 
 
        .stb_i(stb),            // strobe
 
 
 
        .we_i(we),                      // 1 = write
 
 
 
        .adr_i(adr),            // register address
 
 
 
        .dat_i(cpu_dato[7:0]),   // data input bus
 
 
 
        .dat_o(uart_dato),          // data output bus
 
 
 
        .ack_o(uart_ack),               // transfer acknowledge
 
 
 
        .vol_o(),                       // volatile register selected
 
 
 
    .irq_o(uart_irq),           // interrupt request
 
 
 
        //----------------
 
 
 
        .cts_ni(1'b0),          // clear to send - active low - (flow control)
 
 
 
        .rts_no(),      // request to send - active low - (flow control)
 
 
 
        .dsr_ni(1'b0),          // data set ready - active low
 
 
 
        .dcd_ni(1'b0),          // data carrier detect - active low
 
 
 
        .dtr_no(),      // data terminal ready - active low
 
 
 
        .rxd_i(uart_rxd),       // serial data in
 
 
 
        .txd_o(),                       // serial data out
 
 
 
    .data_present_o(),
 
 
 
    .baud16_clk(baud16)
 
 
 
);
 
 
 
 
 
Ps2Keyboard_sim ukbd
 
Ps2Keyboard_sim ukbd
 
(
 
(
 
    .rst_i(rst),
 
    .rst_i(rst),
 
    .clk_i(cpu_clk),
 
    .clk_i(cpu_clk),
 
    .cyc_i(cyc),
 
    .cyc_i(cyc),
Line 103... Line 162... 
        .border(),
 
        .border(),
 
        .rgbIn(),
 
        .rgbIn(),
 
        .rgbOut()
 
        .rgbOut()
 
);
 
);
 
 
 
 
 
rtfTextController3 #(.num(1), .pTextAddress(32'hFFD10000))  tc2
 
rtfTextController3 #(.num(1), .pTextAddress(32'hFFD10000), .pRegAddress(32'hFFDA0040))  tc2
 
(
 
(
 
        .rst_i(rst),
 
        .rst_i(rst),
 
        .clk_i(cpu_clk),
 
        .clk_i(cpu_clk),
 
        .cyc_i(cyc),
 
        .cyc_i(cyc),
 
        .stb_i(stb),
 
        .stb_i(stb),
Line 149... Line 208... 
        .cyc_i(cyc),
 
        .cyc_i(cyc),
 
        .stb_i(stb),
 
        .stb_i(stb),
 
        .ack_o(br_ack),
 
        .ack_o(br_ack),
 
        .adr_i(adr),
 
        .adr_i(adr),
 
        .dat_o(br_dato),
 
        .dat_o(br_dato),
 
        .perr()
 
        .perr(),
 
 
 
        .err1(err1),
 
 
 
        .err2(err2)
 
);
 
);
 
 
 
 
 
wire nmio;
 
wire nmio;
 
Thor_pic upic1
 
Thor_pic upic1
 
(
 
(
Line 165... Line 226... 
        .we_i(we),              // write
 
        .we_i(we),              // write
 
        .adr_i(adr),    // address
 
        .adr_i(adr),    // address
 
        .dat_i(cpu_dato),
 
        .dat_i(cpu_dato),
 
        .dat_o(pic_dato),
 
        .dat_o(pic_dato),
 
        .vol_o(),               // volatile register selected
 
        .vol_o(),               // volatile register selected
 
        .i1(),
 
        .i1(p1000Hz),
 
        .i2(p100Hz),
 
        .i2(p100Hz),
 
        .i3(),
 
        .i3(),
 
        .i4(),
 
        .i4(),
 
        .i5(),
 
        .i5(),
 
        .i6(),
 
        .i6(),
 
        .i7(),
 
        .i7(uart_irq),
 
        .i8(),
 
        .i8(),
 
        .i9(),
 
        .i9(),
 
        .i10(),
 
        .i10(),
 
        .i11(),
 
        .i11(),
 
        .i12(),
 
        .i12(),

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