| Line 54... |
Line 54... |
// will get confused. This can be fixed by having a separate did_branchback status register
|
// will get confused. This can be fixed by having a separate did_branchback status register
|
// for each of the fetch buffers.
|
// for each of the fetch buffers.
|
//
|
//
|
// ============================================================================
|
// ============================================================================
|
// __
|
// __
|
// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford
|
// \\__/ o\ (C) 2013-2016 Robert Finch, Stratford
|
// \ __ / All rights reserved.
|
// \ __ / All rights reserved.
|
// \/_// robfinch<remove>@finitron.ca
|
// \/_// robfinch<remove>@finitron.ca
|
// ||
|
// ||
|
//
|
//
|
// This source file is free software: you can redistribute it and/or modify
|
// This source file is free software: you can redistribute it and/or modify
|
| Line 159... |
Line 159... |
output reg [ABW-1:0] adr_o;
|
output reg [ABW-1:0] adr_o;
|
input [DBW-1:0] dat_i;
|
input [DBW-1:0] dat_i;
|
output reg [DBW-1:0] dat_o;
|
output reg [DBW-1:0] dat_o;
|
|
|
integer n,i;
|
integer n,i;
|
|
reg [1:0] mode;
|
reg [DBW/8-1:0] rsel;
|
reg [DBW/8-1:0] rsel;
|
reg [3:0] cstate;
|
reg [3:0] cstate;
|
reg [ABW:0] pc; // program counter (virtual)
|
reg [ABW:0] pc; // program counter (virtual)
|
wire [ABW-1:0] ppc; // physical pc address
|
wire [ABW-1:0] ppc; // physical pc address
|
reg [ABW-1:0] interrupt_pc; // working register for interrupt pc
|
reg [ABW-1:0] interrupt_pc; // working register for interrupt pc
|
| Line 646... |
Line 647... |
assign dbg_stat1x = {dbg_stat3,dbg_stat2,dbg_stat1,dbg_stat0};
|
assign dbg_stat1x = {dbg_stat3,dbg_stat2,dbg_stat1,dbg_stat0};
|
wire debug_on = |dbg_ctrl[3:0]|dbg_ctrl[7];
|
wire debug_on = |dbg_ctrl[3:0]|dbg_ctrl[7];
|
|
|
reg [11:0] spr_bir;
|
reg [11:0] spr_bir;
|
|
|
|
always @(StatusHWI or StatusDBG or StatusEXL)
|
|
if (StatusHWI)
|
|
mode = 2'd1;
|
|
else if (StatusDBG)
|
|
mode = 2'd3;
|
|
else if (StatusEXL)
|
|
mode = 2'd2;
|
|
else
|
|
mode = 2'd0;
|
|
|
//
|
//
|
// BRANCH-MISS LOGIC: livetarget
|
// BRANCH-MISS LOGIC: livetarget
|
//
|
//
|
// livetarget implies that there is a not-to-be-stomped instruction that targets the register in question
|
// livetarget implies that there is a not-to-be-stomped instruction that targets the register in question
|
// therefore, if it is zero it implies the rf_v value should become VALID on a branchmiss
|
// therefore, if it is zero it implies the rf_v value should become VALID on a branchmiss
|
| Line 953... |
Line 964... |
wire [3:0] Pn0 = fetchbuf0_instr[7:4];
|
wire [3:0] Pn0 = fetchbuf0_instr[7:4];
|
wire [3:0] Pt0 = fetchbuf0_instr[11:8];
|
wire [3:0] Pt0 = fetchbuf0_instr[11:8];
|
wire [3:0] Pn1 = fetchbuf1_instr[7:4];
|
wire [3:0] Pn1 = fetchbuf1_instr[7:4];
|
wire [3:0] Pt1 = fetchbuf1_instr[11:8];
|
wire [3:0] Pt1 = fetchbuf1_instr[11:8];
|
|
|
|
wire [6:0] r27 = 7'd27 + mode;
|
|
|
function [6:0] fnRa;
|
function [6:0] fnRa;
|
input [63:0] isn;
|
input [63:0] isn;
|
case(isn[15:8])
|
case(isn[15:8])
|
`RTS2: fnRa = 7'h51;
|
`RTS2: fnRa = 7'h51;
|
`RTI: fnRa = 7'h5E;
|
`RTI: fnRa = 7'h5E;
|
| Line 965... |
Line 978... |
`JSR,`JSRS,`JSRZ,`SYS,`INT,`RTS:
|
`JSR,`JSRS,`JSRZ,`SYS,`INT,`RTS:
|
fnRa = {3'h5,isn[23:20]};
|
fnRa = {3'h5,isn[23:20]};
|
`TLB: fnRa = {1'b0,isn[29:24]};
|
`TLB: fnRa = {1'b0,isn[29:24]};
|
`P: fnRa = 7'h70;
|
`P: fnRa = 7'h70;
|
`LOOP: fnRa = 7'h73;
|
`LOOP: fnRa = 7'h73;
|
`PUSH: fnRa = km ? 7'd31 : 7'd27;
|
`PUSH: fnRa = r27;
|
`ifdef STACKOPS
|
`ifdef STACKOPS
|
`PEA,`POP,`LINK: fnRa = km ? 7'd31 : 7'd27;
|
`PEA,`POP,`LINK: fnRa = r27;
|
`endif
|
`endif
|
`MFSPR,`MOVS: fnRa = {1'b1,isn[`INSTRUCTION_RA]};
|
`MFSPR,`MOVS:
|
default: fnRa = {1'b0,isn[`INSTRUCTION_RA]};
|
if (isn[`INSTRUCTION_RA]==`USP)
|
|
fnRa = 7'd27;
|
|
else
|
|
fnRa = {1'b1,isn[`INSTRUCTION_RA]};
|
|
default:
|
|
if (isn[`INSTRUCTION_RA]==6'd27)
|
|
fnRa = r27;
|
|
else
|
|
fnRa = {1'b0,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [6:0] fnRb;
|
function [6:0] fnRb;
|
input [63:0] isn;
|
input [63:0] isn;
|
case(isn[15:8])
|
case(isn[15:8])
|
// `LOOP: fnRb = 7'h73;
|
// `LOOP: fnRb = 7'h73;
|
// `RTS,`STP,`TLB,`POP: fnRb = 7'd0;
|
// `RTS,`STP,`TLB,`POP: fnRb = 7'd0;
|
`JSR,`JSRS,`JSRZ,`SYS,`INT:
|
`JSR,`JSRS,`JSRZ,`SYS,`INT:
|
fnRb = {3'h5,isn[23:20]};
|
fnRb = {3'h5,isn[23:20]};
|
`SWS: fnRb = {1'b1,isn[27:22]};
|
`SWS: if (isn[27:22]==`USP)
|
|
fnRb = {1'b0,6'd27};
|
|
else
|
|
fnRb = {1'b1,isn[27:22]};
|
`PUSH: fnRb = isn[22:16];
|
`PUSH: fnRb = isn[22:16];
|
`ifdef STACKOPS
|
`ifdef STACKOPS
|
`LINK: fnRb = {1'b0,isn[27:22]};
|
`LINK: fnRb = {1'b0,isn[27:22]};
|
`PEA: fnRb = {1'b0,isn[21:16]};
|
`PEA: fnRb = {1'b0,isn[21:16]};
|
`endif
|
`endif
|
default: fnRb = {1'b0,isn[`INSTRUCTION_RB]};
|
default:
|
|
if (isn[`INSTRUCTION_RB]==6'd27)
|
|
fnRb = r27;
|
|
else
|
|
fnRb = {1'b0,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [6:0] fnRc;
|
function [6:0] fnRc;
|
input [63:0] isn;
|
input [63:0] isn;
|
|
if (isn[`INSTRUCTION_RC]==6'd27)
|
|
fnRc = r27;
|
|
else
|
fnRc = {1'b0,isn[`INSTRUCTION_RC]};
|
fnRc = {1'b0,isn[`INSTRUCTION_RC]};
|
endfunction
|
endfunction
|
|
|
function [3:0] fnCar;
|
function [3:0] fnCar;
|
input [63:0] isn;
|
input [63:0] isn;
|
| Line 1072... |
Line 1103... |
case(func)
|
case(func)
|
`CNTLZ,`CNTLO,`CNTPOP: fnIsAlu0Op = `TRUE;
|
`CNTLZ,`CNTLO,`CNTPOP: fnIsAlu0Op = `TRUE;
|
`ABS,`SGN,`ZXB,`ZXC,`ZXH,`SXB,`SXC,`SXH: fnIsAlu0Op = `TRUE;
|
`ABS,`SGN,`ZXB,`ZXC,`ZXH,`SXB,`SXC,`SXH: fnIsAlu0Op = `TRUE;
|
default: fnIsAlu0Op = `FALSE;
|
default: fnIsAlu0Op = `FALSE;
|
endcase
|
endcase
|
|
`R2: fnIsAlu0Op = `TRUE;
|
`RR:
|
`RR:
|
case(func)
|
case(func)
|
`DIV,`DIVU: fnIsAlu0Op = `TRUE;
|
`DIV,`DIVU: fnIsAlu0Op = `TRUE;
|
`MOD,`MODU: fnIsAlu0Op = `TRUE;
|
`MOD,`MODU: fnIsAlu0Op = `TRUE;
|
`MIN,`MAX: fnIsAlu0Op = `TRUE;
|
`MIN,`MAX: fnIsAlu0Op = `TRUE;
|
| Line 1227... |
Line 1259... |
`SHIFT:
|
`SHIFT:
|
if (func>=6'h10)
|
if (func>=6'h10)
|
fnSource2_v = `TRUE;
|
fnSource2_v = `TRUE;
|
else
|
else
|
fnSource2_v = `FALSE;
|
fnSource2_v = `FALSE;
|
`CACHE,`LCL,`TLB,`LLA,`LEA,
|
`CACHE,`LCL,`TLB,`LLA,
|
`LVB,`LVC,`LVH,`LVW,`LVWAR,
|
`LVB,`LVC,`LVH,`LVW,`LVWAR,
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWS,`STI,`INC:
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWS,`STI,`INC:
|
fnSource2_v = 1'b1;
|
fnSource2_v = 1'b1;
|
`JSR,`JSRS,`JSRZ,`SYS,`INT,`RTS,`RTS2:
|
`JSR,`JSRS,`JSRZ,`SYS,`INT,`RTS,`RTS2:
|
fnSource2_v = 1'b1;
|
fnSource2_v = 1'b1;
|
| Line 1253... |
Line 1285... |
// a valid status.
|
// a valid status.
|
// 1 if the the operand is automatically valid,
|
// 1 if the the operand is automatically valid,
|
// 0 if we need a RF value
|
// 0 if we need a RF value
|
function fnSource3_v;
|
function fnSource3_v;
|
input [7:0] opcode;
|
input [7:0] opcode;
|
|
input [5:0] func;
|
case(opcode)
|
case(opcode)
|
|
`RR:
|
|
case(func)
|
|
`CHK: fnSource3_v = 1'b0;
|
|
default: fnSource3_v = 1'b1;
|
|
endcase
|
`SBX,`SCX,`SHX,`SWX,`CAS,`STMV,`STCMP,`STFND: fnSource3_v = 1'b0;
|
`SBX,`SCX,`SHX,`SWX,`CAS,`STMV,`STCMP,`STFND: fnSource3_v = 1'b0;
|
`MUX: fnSource3_v = 1'b0;
|
`MUX: fnSource3_v = 1'b0;
|
default: fnSource3_v = 1'b1;
|
default: fnSource3_v = 1'b1;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function fnSourceT_v;
|
function fnSourceT_v;
|
input [7:0] opcode;
|
input [7:0] opcode;
|
|
input [5:0] func;
|
case(opcode)
|
case(opcode)
|
|
`RR:
|
|
case(func)
|
|
`CHK: fnSourceT_v = 1'b1;
|
|
default: fnSourceT_v = 1'b0;
|
|
endcase
|
// BR
|
// BR
|
8'h30,8'h31,8'h32,8'h33,
|
8'h30,8'h31,8'h32,8'h33,
|
8'h34,8'h35,8'h36,8'h37,
|
8'h34,8'h35,8'h36,8'h37,
|
8'h38,8'h39,8'h3A,8'h3B,
|
8'h38,8'h39,8'h3A,8'h3B,
|
8'h3C,8'h3D,8'h3E,8'h3F,
|
8'h3C,8'h3D,8'h3E,8'h3F,
|
`SB,`SC,`SH,`SW,`SBX,`SCX,`SHX,`SWX,`SWS,
|
`SB,`SC,`SH,`SW,`SBX,`SCX,`SHX,`SWX,`SWS,
|
`CACHE,
|
`CACHE,`CHKI,
|
`SEI,`CLI,`NOP,`STP,`RTI,`RTD,`RTE,
|
`SEI,`CLI,`NOP,`STP,`RTI,`RTD,`RTE,
|
`MEMSB,`MEMDB,`SYNC:
|
`MEMSB,`MEMDB,`SYNC:
|
fnSourceT_v = 1'b1;
|
fnSourceT_v = 1'b1;
|
default: fnSourceT_v = 1'b0;
|
default: fnSourceT_v = 1'b0;
|
endcase
|
endcase
|
| Line 1300... |
Line 1344... |
`SHIFT:
|
`SHIFT:
|
if (ins[39:38]==2'h1) // shift immediate
|
if (ins[39:38]==2'h1) // shift immediate
|
fnNumReadPorts = 3'd1;
|
fnNumReadPorts = 3'd1;
|
else
|
else
|
fnNumReadPorts = 3'd2;
|
fnNumReadPorts = 3'd2;
|
`CACHE,`LCL,`TLB,`LLA,`LEA,
|
`CACHE,`LCL,`TLB,`LLA,
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,`LVWAR,`LWS,`INC:
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,`LVWAR,`LWS,`INC:
|
fnNumReadPorts = 3'd1;
|
fnNumReadPorts = 3'd1;
|
`JSR,`JSRS,`JSRZ,`SYS,`INT,`RTS,`RTS2,`BR:
|
`JSR,`JSRS,`JSRZ,`SYS,`INT,`RTS,`RTS2,`BR:
|
fnNumReadPorts = 3'd1;
|
fnNumReadPorts = 3'd1;
|
`SBX,`SCX,`SHX,`SWX,
|
`SBX,`SCX,`SHX,`SWX,
|
`MUX,`CAS,`STMV,`STCMP:
|
`MUX,`CAS,`STMV,`STCMP:
|
fnNumReadPorts = 3'd3;
|
fnNumReadPorts = 3'd3;
|
`MTSPR,`MFSPR,`POP,`UNLINK: fnNumReadPorts = 3'd1;
|
`MTSPR,`MFSPR,`POP,`UNLINK: fnNumReadPorts = 3'd1;
|
`STFND: fnNumReadPorts = 3'd2; // *** TLB reads on Rb we say 2 for simplicity
|
`STFND: fnNumReadPorts = 3'd2; // *** TLB reads on Rb we say 2 for simplicity
|
|
`RR:
|
|
case(ins[39:34])
|
|
`CHK: fnNumReadPorts = 3'd3;
|
|
default: fnNumReadPorts = 3'd2;
|
|
endcase
|
`BITFIELD:
|
`BITFIELD:
|
case(ins[43:40])
|
case(ins[43:40])
|
`BFSET,`BFCLR,`BFCHG,`BFEXT,`BFEXTU,`BFINSI:
|
`BFSET,`BFCLR,`BFCHG,`BFEXT,`BFEXTU,`BFINSI:
|
fnNumReadPorts = 3'd1;
|
fnNumReadPorts = 3'd1;
|
`BFINS: fnNumReadPorts = 3'd2;
|
`BFINS: fnNumReadPorts = 3'd2;
|
| Line 1450... |
Line 1499... |
.d({fetchbuf1_pc,fetcbuf0_pc}),
|
.d({fetchbuf1_pc,fetcbuf0_pc}),
|
.q(pc_histo)
|
.q(pc_histo)
|
);
|
);
|
`endif
|
`endif
|
|
|
Thor_icachemem #(.DBW(DBW),.ABW(ABW)) uicm1
|
Thor_icachemem #(.DBW(DBW),.ABW(ABW),.ECC(1'b0)) uicm1
|
(
|
(
|
.wclk(clk),
|
.wclk(clk),
|
.wce(cstate==ICACHE1),
|
.wce(cstate==ICACHE1),
|
.wr(ack_i|err_i),
|
.wr(ack_i|err_i),
|
.wa(adr_o),
|
.wa(adr_o),
|
.wd({err_i,dat_i}),
|
.wd(dat_i),
|
.rclk(~clk),
|
.rclk(~clk),
|
.pc(ppc),
|
.pc(ppc),
|
.insn(insn)
|
.insn(insn)
|
);
|
);
|
|
|
| Line 1496... |
Line 1545... |
.wclk(clk),
|
.wclk(clk),
|
.wce(whit || cstate==DCACHE1),
|
.wce(whit || cstate==DCACHE1),
|
.wr(ack_i|err_i),
|
.wr(ack_i|err_i),
|
.sel(whit ? sel_o : 8'hFF),
|
.sel(whit ? sel_o : 8'hFF),
|
.wa(adr_o),
|
.wa(adr_o),
|
.wd(whit ? dat_o : dat_i),
|
.wd(whit ? dat_o : dat_i[DBW-1:0]),
|
.rclk(~clk),
|
.rclk(~clk),
|
.rce(1'b1),
|
.rce(1'b1),
|
.ra(pea),
|
.ra(pea),
|
.o(cdat)
|
.o(cdat)
|
);
|
);
|
| Line 1585... |
Line 1634... |
fnTargetReg = 7'h000;
|
fnTargetReg = 7'h000;
|
else
|
else
|
case(fnOpcode(ir))
|
case(fnOpcode(ir))
|
`POP: fnTargetReg = ir[22:16];
|
`POP: fnTargetReg = ir[22:16];
|
`LDI,`ADDUIS,`STS,`LINK,`UNLINK:
|
`LDI,`ADDUIS,`STS,`LINK,`UNLINK:
|
|
if (ir[21:16]==6'd27)
|
|
fnTargetReg = r27;
|
|
else
|
fnTargetReg = {1'b0,ir[21:16]};
|
fnTargetReg = {1'b0,ir[21:16]};
|
`LDIS:
|
`LDIS:
|
fnTargetReg = {1'b1,ir[21:16]};
|
fnTargetReg = {1'b1,ir[21:16]};
|
`RR:
|
`RR,
|
fnTargetReg = {1'b0,ir[33:28]};
|
`SHIFT,
|
`BCD,
|
`BCD,
|
`LOGIC,`FLOAT,
|
`LOGIC,`FLOAT,
|
`LWX,`LBX,`LBUX,`LCX,`LCUX,`LHX,`LHUX,`STMV,`STCMP,`STFND:
|
`LWX,`LBX,`LBUX,`LCX,`LCUX,`LHX,`LHUX,`STMV,`STCMP,`STFND:
|
fnTargetReg = {1'b0,ir[33:28]};
|
if (ir[33:28]==6'd27)
|
`SHIFT:
|
fnTargetReg = r27;
|
|
else
|
fnTargetReg = {1'b0,ir[33:28]};
|
fnTargetReg = {1'b0,ir[33:28]};
|
`R,`R2,`DOUBLE_R,`SINGLE_R,
|
`R,`R2,`DOUBLE_R,`SINGLE_R,
|
`ADDI,`ADDUI,`SUBI,`SUBUI,
|
`ADDI,`ADDUI,`SUBI,`SUBUI,
|
`MULI,`MULUI,`DIVI,`DIVUI,`MODI,`MODUI,
|
`MULI,`MULUI,`DIVI,`DIVUI,`MODI,`MODUI,
|
`_2ADDUI,`_4ADDUI,`_8ADDUI,`_16ADDUI,
|
`_2ADDUI,`_4ADDUI,`_8ADDUI,`_16ADDUI,
|
`ANDI,`ORI,`EORI,`LLA,`LEA,
|
`ANDI,`ORI,`EORI,`LLA,
|
`LVB,`LVC,`LVH,`LVW,`LVWAR,
|
`LVB,`LVC,`LVH,`LVW,`LVWAR,
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LINK:
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LINK,
|
|
`BITFIELD,`MFSPR:
|
|
if (ir[27:22]==6'd27)
|
|
fnTargetReg = r27;
|
|
else
|
fnTargetReg = {1'b0,ir[27:22]};
|
fnTargetReg = {1'b0,ir[27:22]};
|
`CAS:
|
`CAS:
|
fnTargetReg = {1'b0,ir[39:34]};
|
fnTargetReg = {1'b0,ir[39:34]};
|
`BITFIELD:
|
|
fnTargetReg = {1'b0,ir[27:22]};
|
|
`TLB:
|
`TLB:
|
if (ir[19:16]==`TLB_RDREG)
|
if (ir[19:16]==`TLB_RDREG)
|
fnTargetReg = {1'b0,ir[29:24]};
|
fnTargetReg = {1'b0,ir[29:24]};
|
else
|
else
|
fnTargetReg = 7'h00;
|
fnTargetReg = 7'h00;
|
`MFSPR:
|
|
fnTargetReg = {1'b0,ir[27:22]};
|
|
`BITI:
|
`BITI:
|
fnTargetReg = {3'h4,ir[25:22]};
|
fnTargetReg = {3'h4,ir[25:22]};
|
// TST
|
// TST
|
8'h00,8'h01,8'h02,8'h03,
|
8'h00,8'h01,8'h02,8'h03,
|
8'h04,8'h05,8'h06,8'h07,
|
8'h04,8'h05,8'h06,8'h07,
|
| Line 1643... |
Line 1696... |
`JMPI:
|
`JMPI:
|
fnTargetReg = {3'h5,ir[25:22]};
|
fnTargetReg = {3'h5,ir[25:22]};
|
`JMPIX:
|
`JMPIX:
|
fnTargetReg = {3'h5,ir[31:28]};
|
fnTargetReg = {3'h5,ir[31:28]};
|
`MTSPR,`MOVS,`LWS:
|
`MTSPR,`MOVS,`LWS:
|
|
if (ir[27:22]==`USP)
|
|
fnTargetReg = {1'b0,6'd27};
|
|
else
|
fnTargetReg = {1'b1,ir[27:22]};
|
fnTargetReg = {1'b1,ir[27:22]};
|
/*
|
/*
|
if (ir[27:26]==2'h1) // Move to code address register
|
if (ir[27:26]==2'h1) // Move to code address register
|
fnTargetReg = {3'h5,ir[25:22]};
|
fnTargetReg = {3'h5,ir[25:22]};
|
else if (ir[27:26]==2'h2) // Move to seg. reg.
|
else if (ir[27:26]==2'h2) // Move to seg. reg.
|
| Line 1654... |
Line 1710... |
else if (ir[27:22]==6'h04)
|
else if (ir[27:22]==6'h04)
|
fnTargetReg = 7'h70;
|
fnTargetReg = 7'h70;
|
else
|
else
|
fnTargetReg = 7'h00;
|
fnTargetReg = 7'h00;
|
*/
|
*/
|
`PUSH: fnTargetReg = km ? 7'd31 : 7'd27;
|
`PUSH: fnTargetReg = r27;
|
`LOOP: fnTargetReg = 7'h73;
|
`LOOP: fnTargetReg = 7'h73;
|
`STP: fnTargetReg = 7'h7F;
|
`STP: fnTargetReg = 7'h7F;
|
`P: fnTargetReg = 7'h70;
|
`P: fnTargetReg = 7'h70;
|
default: fnTargetReg = 7'h00;
|
default: fnTargetReg = 7'h00;
|
endcase
|
endcase
|
| Line 1733... |
Line 1789... |
input [7:0] opcode;
|
input [7:0] opcode;
|
case(opcode)
|
case(opcode)
|
`BFCLR,`BFSET,`BFCHG,`BFEXT,`BFEXTU,`BFINS,
|
`BFCLR,`BFSET,`BFCHG,`BFEXT,`BFEXTU,`BFINS,
|
`LDI,`LDIS,`ADDUIS,
|
`LDI,`LDIS,`ADDUIS,
|
`ADDI,`SUBI,`ADDUI,`SUBUI,`MULI,`MULUI,`DIVI,`DIVUI,`MODI,`MODUI,
|
`ADDI,`SUBI,`ADDUI,`SUBUI,`MULI,`MULUI,`DIVI,`DIVUI,`MODI,`MODUI,
|
`_2ADDUI,`_4ADDUI,`_8ADDUI,`_16ADDUI,
|
`_2ADDUI,`_4ADDUI,`_8ADDUI,`_16ADDUI,`CHKI,
|
// CMPI
|
// CMPI
|
8'h20,8'h21,8'h22,8'h23,
|
8'h20,8'h21,8'h22,8'h23,
|
8'h24,8'h25,8'h26,8'h27,
|
8'h24,8'h25,8'h26,8'h27,
|
8'h28,8'h29,8'h2A,8'h2B,
|
8'h28,8'h29,8'h2A,8'h2B,
|
8'h2C,8'h2D,8'h2E,8'h2F,
|
8'h2C,8'h2D,8'h2E,8'h2F,
|
| Line 1801... |
Line 1857... |
default: fnCanException = `FALSE;
|
default: fnCanException = `FALSE;
|
endcase
|
endcase
|
`SINGLE_R:
|
`SINGLE_R:
|
if (func==`FTX) fnCanException = `TRUE;
|
if (func==`FTX) fnCanException = `TRUE;
|
else fnCanException = `FALSE;
|
else fnCanException = `FALSE;
|
`ADDI,`SUBI,`DIVI,`MODI,`MULI:
|
`ADDI,`SUBI,`DIVI,`MODI,`MULI,`CHKI:
|
fnCanException = `TRUE;
|
fnCanException = `TRUE;
|
`RR:
|
`RR:
|
if (func==`ADD || func==`SUB || func==`MUL || func==`DIV || func==`MOD)
|
if (func==`ADD || func==`SUB || func==`MUL || func==`DIV || func==`MOD || func==`CHK)
|
fnCanException = `TRUE;
|
fnCanException = `TRUE;
|
else
|
else
|
fnCanException = `FALSE;
|
fnCanException = `FALSE;
|
`TLB,`RTI,`RTD,`RTE,`CLI,`SEI:
|
`TLB,`RTI,`RTD,`RTE,`CLI,`SEI:
|
fnCanException = `TRUE;
|
fnCanException = `TRUE;
|
| Line 1949... |
Line 2005... |
begin
|
begin
|
fnIsRFW = // General registers
|
fnIsRFW = // General registers
|
opcode==`LB || opcode==`LBU || opcode==`LC || opcode==`LCU || opcode==`LH || opcode==`LHU || opcode==`LW ||
|
opcode==`LB || opcode==`LBU || opcode==`LC || opcode==`LCU || opcode==`LH || opcode==`LHU || opcode==`LW ||
|
opcode==`LBX || opcode==`LBUX || opcode==`LCX || opcode==`LCUX || opcode==`LHX || opcode==`LHUX || opcode==`LWX ||
|
opcode==`LBX || opcode==`LBUX || opcode==`LCX || opcode==`LCUX || opcode==`LHX || opcode==`LHUX || opcode==`LWX ||
|
opcode==`LVB || opcode==`LVH || opcode==`LVC || opcode==`LVW || opcode==`LVWAR || opcode==`SWCR ||
|
opcode==`LVB || opcode==`LVH || opcode==`LVC || opcode==`LVW || opcode==`LVWAR || opcode==`SWCR ||
|
opcode==`STP || opcode==`LLA || opcode==`LLAX || opcode==`LEA ||
|
opcode==`STP || opcode==`LLA || opcode==`LLAX ||
|
opcode==`CAS || opcode==`LWS || opcode==`STMV || opcode==`STCMP || opcode==`STFND ||
|
opcode==`CAS || opcode==`LWS || opcode==`STMV || opcode==`STCMP || opcode==`STFND ||
|
opcode==`STS || opcode==`PUSH || opcode==`POP || opcode==`LINK || opcode==`UNLINK ||
|
opcode==`STS || opcode==`PUSH || opcode==`POP || opcode==`LINK || opcode==`UNLINK ||
|
opcode==`JMPI || opcode==`JMPIX ||
|
opcode==`JMPI || opcode==`JMPIX ||
|
opcode==`ADDI || opcode==`SUBI || opcode==`ADDUI || opcode==`SUBUI ||
|
opcode==`ADDI || opcode==`SUBI || opcode==`ADDUI || opcode==`SUBUI ||
|
opcode==`MULI || opcode==`MULUI || opcode==`DIVI || opcode==`DIVUI || opcode==`MODI || opcode==`MODUI ||
|
opcode==`MULI || opcode==`MULUI || opcode==`DIVI || opcode==`DIVUI || opcode==`MODI || opcode==`MODUI ||
|
| Line 2018... |
Line 2074... |
input [5:0] fn;
|
input [5:0] fn;
|
casex(op)
|
casex(op)
|
8'h40:
|
8'h40:
|
if (fn > 6'h17)
|
if (fn > 6'h17)
|
fnIsIllegal = `TRUE;
|
fnIsIllegal = `TRUE;
|
else if (fn==6'hC || fn==6'hD || fn==6'hE || fn==6'hF || fn==6'h12 || fn==6'h14 || fn==6'h15 || fn==6'h16)
|
else if (fn==6'hC || fn==6'hD || fn==6'hE || fn==6'hF || fn==6'h12 || fn==6'h15 || fn==6'h16)
|
fnIsIllegal = `TRUE;
|
fnIsIllegal = `TRUE;
|
else fnIsIllegal = `FALSE;
|
else fnIsIllegal = `FALSE;
|
8'h41:
|
8'h41:
|
if (fn > 6'd3) fnIsIllegal = `TRUE;
|
if (fn > 6'd3) fnIsIllegal = `TRUE;
|
else fnIsIllegal = `FALSE;
|
else fnIsIllegal = `FALSE;
|
| Line 2061... |
Line 2117... |
if (fn > 4'd2)
|
if (fn > 4'd2)
|
fnIsIllegal = `TRUE;
|
fnIsIllegal = `TRUE;
|
else
|
else
|
fnIsIllegal = `FALSE;
|
fnIsIllegal = `FALSE;
|
8'h43,8'h44,8'h45: fnIsIllegal = `TRUE;
|
8'h43,8'h44,8'h45: fnIsIllegal = `TRUE;
|
8'h52,8'h56,8'h57,8'h59,8'h5A,8'h5D,8'h5E:
|
8'h52,8'h56,8'h57,8'h59,8'h5A,8'h5C,8'h5E:
|
fnIsIllegal = `TRUE;
|
fnIsIllegal = `TRUE;
|
8'h60,8'h61,8'h62,8'h63,8'h64,8'h65,8'h66,8'h67,8'h68,8'h69:
|
8'h60,8'h61,8'h62,8'h63,8'h64,8'h65,8'h66,8'h67,8'h68,8'h69:
|
fnIsIllegal = `TRUE;
|
fnIsIllegal = `TRUE;
|
8'h73,8'h74,8'h75,8'h76,8'h7A,8'h7B,8'h7C,8'h7D,8'h7E,8'h7F:
|
8'h73,8'h74,8'h75,8'h76,8'h7A,8'h7B,8'h7C,8'h7D,8'h7E,8'h7F:
|
fnIsIllegal = `TRUE;
|
fnIsIllegal = `TRUE;
|
| Line 2583... |
Line 2639... |
`RTS: fnImm = insn[19:16];
|
`RTS: fnImm = insn[19:16];
|
`RTD,`RTE,`RTI,`RTS2,`JSRZ,`STMV,`STCMP,`STFND,`CACHE,`STS: fnImm = 64'h0;
|
`RTD,`RTE,`RTI,`RTS2,`JSRZ,`STMV,`STCMP,`STFND,`CACHE,`STS: fnImm = 64'h0;
|
`STI: fnImm = {{58{insn[33]}},insn[33:28]};
|
`STI: fnImm = {{58{insn[33]}},insn[33:28]};
|
`PUSH: fnImm = 64'hFFFFFFFFFFFFFFF8; //-8
|
`PUSH: fnImm = 64'hFFFFFFFFFFFFFFF8; //-8
|
//`LINK: fnImm = {insn[39:28],3'b000};
|
//`LINK: fnImm = {insn[39:28],3'b000};
|
`JMPI,`LLA,`LEA,
|
`JMPI,`LLA,
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,`LVWAR,
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,`LVWAR,
|
`SB,`SC,`SH,`SW,`SWCR,`LWS,`SWS,`INC,`LCL,`PEA:
|
`SB,`SC,`SH,`SW,`SWCR,`LWS,`SWS,`INC,`LCL,`PEA:
|
fnImm = {{55{insn[36]}},insn[36:28]};
|
fnImm = {{55{insn[36]}},insn[36:28]};
|
default:
|
default:
|
fnImm = {{52{insn[39]}},insn[39:28]};
|
fnImm = {{52{insn[39]}},insn[39:28]};
|
| Line 2617... |
Line 2673... |
`STI: fnImm8 = insn[35:28];
|
`STI: fnImm8 = insn[35:28];
|
`PUSH: fnImm8 = 8'hF8;
|
`PUSH: fnImm8 = 8'hF8;
|
`ifdef STACKOPS
|
`ifdef STACKOPS
|
`LINK: fnImm8 = {insn[32:28],3'b000};
|
`LINK: fnImm8 = {insn[32:28],3'b000};
|
`endif
|
`endif
|
`JMPI,`LLA,`LEA,
|
`JMPI,`LLA,
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,`LVWAR,
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,`LVWAR,
|
`SB,`SC,`SH,`SW,`SWCR,`LWS,`SWS,`INC,`LCL,`PEA:
|
`SB,`SC,`SH,`SW,`SWCR,`LWS,`SWS,`INC,`LCL,`PEA:
|
fnImm8 = insn[35:28];
|
fnImm8 = insn[35:28];
|
default: fnImm8 = insn[35:28];
|
default: fnImm8 = insn[35:28];
|
endcase
|
endcase
|
| Line 2653... |
Line 2709... |
fnImmMSB = 1'b0; // RTS is unsigned
|
fnImmMSB = 1'b0; // RTS is unsigned
|
`PUSH: fnImmMSB = 1'b1;
|
`PUSH: fnImmMSB = 1'b1;
|
`LBX,`LBUX,`LCX,`LCUX,`LHX,`LHUX,`LWX,
|
`LBX,`LBUX,`LCX,`LCUX,`LHX,`LHUX,`LWX,
|
`SBX,`SCX,`SHX,`SWX:
|
`SBX,`SCX,`SHX,`SWX:
|
fnImmMSB = insn[47];
|
fnImmMSB = insn[47];
|
`JMPI,`LLA,`LEA,
|
`JMPI,`LLA,
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,
|
`SB,`SC,`SH,`SW,`SWCR,`STI,`LWS,`SWS,`INC,`LCL,`PEA:
|
`SB,`SC,`SH,`SW,`SWCR,`STI,`LWS,`SWS,`INC,`LCL,`PEA:
|
fnImmMSB = insn[36];
|
fnImmMSB = insn[36];
|
default:
|
default:
|
fnImmMSB = insn[39];
|
fnImmMSB = insn[39];
|
| Line 2745... |
Line 2801... |
|
|
function fnIsKMOnlyReg;
|
function fnIsKMOnlyReg;
|
input [6:0] regx;
|
input [6:0] regx;
|
`ifdef PRIVCHKS
|
`ifdef PRIVCHKS
|
fnIsKMOnlyReg = regx==7'd28 || regx==7'd29 || regx==7'd30 || regx==7'd31 ||
|
fnIsKMOnlyReg = regx==7'd28 || regx==7'd29 || regx==7'd30 || regx==7'd31 ||
|
regx==7'h5B || regx==7'h5C || regx==7'h5D || regx==7'h5E ||
|
regx==7'h5B || regx==7'h5C || regx==7'h5D || regx==7'h5E
|
regx==7'h60 || regx==7'h68;
|
;
|
`else
|
`else
|
fnIsKMOnlyReg = `FALSE;
|
fnIsKMOnlyReg = `FALSE;
|
`endif
|
`endif
|
endfunction
|
endfunction
|
|
|
| Line 3817... |
Line 3873... |
end
|
end
|
end
|
end
|
|
|
if (alu0_v) begin
|
if (alu0_v) begin
|
if (|alu0_exc)
|
if (|alu0_exc)
|
set_exception(alu0_id, alu0_exc==`EXC_DBZ ? 8'd241 : 8'h00);
|
set_exception(alu0_id,
|
|
alu0_exc==`EXC_PRIV ? 8'd245 :
|
|
alu0_exc==`EXC_DBZ ? 8'd241 :
|
|
alu0_exc==`EXC_CHK ? 8'd239 : 8'h00);
|
else begin
|
else begin
|
if (iqentry_op[alu0_id[2:0]]!=`IMM)
|
if (iqentry_op[alu0_id[2:0]]!=`IMM)
|
iqentry_done[ alu0_id[2:0] ] <= (!iqentry_mem[ alu0_id[2:0] ] || !alu0_cmt);
|
iqentry_done[ alu0_id[2:0] ] <= (!iqentry_mem[ alu0_id[2:0] ] || !alu0_cmt);
|
if (iqentry_jmpi[alu0_id[2:0]] && alu0_cmt)
|
if (iqentry_jmpi[alu0_id[2:0]] && alu0_cmt)
|
iqentry_res [alu0_id[2:0]] <= alu0_pc + alu0_insnsz;
|
iqentry_res [alu0_id[2:0]] <= alu0_pc + alu0_insnsz;
|
| Line 3846... |
Line 3905... |
end
|
end
|
end
|
end
|
|
|
if (alu1_v) begin
|
if (alu1_v) begin
|
if (|alu1_exc)
|
if (|alu1_exc)
|
set_exception(alu1_id, alu1_exc==`EXC_DBZ ? 8'd241 : 8'h00);
|
set_exception(alu1_id,
|
|
alu1_exc==`EXC_PRIV ? 8'd245 :
|
|
alu1_exc==`EXC_DBZ ? 8'd241 :
|
|
alu1_exc==`EXC_CHK ? 8'd239 : 8'h00);
|
else begin
|
else begin
|
if (iqentry_op[alu1_id[2:0]]!=`IMM)
|
if (iqentry_op[alu1_id[2:0]]!=`IMM)
|
iqentry_done[ alu1_id[2:0] ] <= (!iqentry_mem[ alu1_id[2:0] ] || !alu1_cmt);
|
iqentry_done[ alu1_id[2:0] ] <= (!iqentry_mem[ alu1_id[2:0] ] || !alu1_cmt);
|
if (iqentry_jmpi[alu1_id[2:0]] && alu1_cmt)
|
if (iqentry_jmpi[alu1_id[2:0]] && alu1_cmt)
|
iqentry_res [alu1_id[2:0]] <= alu1_pc + alu1_insnsz;
|
iqentry_res [alu1_id[2:0]] <= alu1_pc + alu1_insnsz;
|
| Line 4689... |
Line 4751... |
dram_tgt <= dram0_tgt;
|
dram_tgt <= dram0_tgt;
|
dram_exc <= (err_i & dram0_tgt!=7'd0) ? `EXC_DBE : `EXC_NONE;//dram0_exc;
|
dram_exc <= (err_i & dram0_tgt!=7'd0) ? `EXC_DBE : `EXC_NONE;//dram0_exc;
|
if (dram0_op==`SWCR)
|
if (dram0_op==`SWCR)
|
dram_bus <= {63'd0,resv_i};
|
dram_bus <= {63'd0,resv_i};
|
else
|
else
|
dram_bus <= fnDatai(dram0_op,dram0_fn,dat_i,rsel);
|
dram_bus <= fnDatai(dram0_op,dram0_fn,dat_i[DBW-1:0],rsel);
|
dram0_owns_bus <= `FALSE;
|
dram0_owns_bus <= `FALSE;
|
wb_nack();
|
wb_nack();
|
dram0 <= 3'd7;
|
dram0 <= 3'd7;
|
case(dram0_op)
|
case(dram0_op)
|
`ifdef STRINGOPS
|
`ifdef STRINGOPS
|
| Line 4716... |
Line 4778... |
dram0 <= 3'd1;
|
dram0 <= 3'd1;
|
dram0_owns_bus <= `TRUE;
|
dram0_owns_bus <= `TRUE;
|
if (stmv_flag) begin
|
if (stmv_flag) begin
|
dram0_addr <= src_addr + index;
|
dram0_addr <= src_addr + index;
|
if (dram0_op==`STCMP) begin
|
if (dram0_op==`STCMP) begin
|
if (dram0_data != fnDatai(dram0_op,dram0_fn,dat_i,rsel)) begin
|
if (dram0_data != fnDatai(dram0_op,dram0_fn,dat_i[DBW-1:0],rsel)) begin
|
lc <= 64'd0;
|
lc <= 64'd0;
|
dram0 <= 3'd7;
|
dram0 <= 3'd7;
|
dram_v <= `VAL;
|
dram_v <= `VAL;
|
end
|
end
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
dram0_addr <= dst_addr + index;
|
dram0_addr <= dst_addr + index;
|
dram0_data <= fnDatai(dram0_op,dram0_fn,dat_i,rsel);
|
dram0_data <= fnDatai(dram0_op,dram0_fn,dat_i[DBW-1:0],rsel);
|
end
|
end
|
if (!stmv_flag)
|
if (!stmv_flag)
|
inc_index(dram0_fn);
|
inc_index(dram0_fn);
|
stmv_flag <= ~stmv_flag;
|
stmv_flag <= ~stmv_flag;
|
end
|
end
|
| Line 4740... |
Line 4802... |
end
|
end
|
`STFND:
|
`STFND:
|
if (lc != 0 && !int_pending) begin
|
if (lc != 0 && !int_pending) begin
|
dram0_addr <= src_addr + index;
|
dram0_addr <= src_addr + index;
|
inc_index(dram0_fn);
|
inc_index(dram0_fn);
|
if (dram0_data == fnDatai(dram0_op,dram0_fn,dat_i,rsel)) begin
|
if (dram0_data == fnDatai(dram0_op,dram0_fn,dat_i[DBW-1:0],rsel)) begin
|
lc <= 64'd0;
|
lc <= 64'd0;
|
dram_v <= `VAL;
|
dram_v <= `VAL;
|
dram_bus <= index;
|
dram_bus <= index;
|
end
|
end
|
else
|
else
|
| Line 4755... |
Line 4817... |
dram_v <= `VAL;
|
dram_v <= `VAL;
|
dram0_op <= `NOP;
|
dram0_op <= `NOP;
|
end
|
end
|
`endif
|
`endif
|
`CAS:
|
`CAS:
|
if (dram0_datacmp == dat_i) begin
|
if (dram0_datacmp == dat_i[DBW-1:0]) begin
|
$display("CAS match");
|
$display("CAS match");
|
dram0_owns_bus <= `TRUE;
|
dram0_owns_bus <= `TRUE;
|
cyc_o <= 1'b1; // hold onto cyc_o
|
cyc_o <= 1'b1; // hold onto cyc_o
|
dram0 <= dram0 + 3'd1;
|
dram0 <= dram0 + 3'd1;
|
end
|
end
|
| Line 4772... |
Line 4834... |
if (stmv_flag) begin
|
if (stmv_flag) begin
|
dram_v <= `VAL;
|
dram_v <= `VAL;
|
dram0 <= 3'd0;
|
dram0 <= 3'd0;
|
end
|
end
|
else begin
|
else begin
|
dram0_data <= fnDatai(dram0_op,dram0_fn,dat_i,rsel);
|
dram0_data <= fnDatai(dram0_op,dram0_fn,dat_i[DBW-1:0],rsel);
|
stmv_flag <= ~stmv_flag;
|
stmv_flag <= ~stmv_flag;
|
dram0 <= 3'd1;
|
dram0 <= 3'd1;
|
end
|
end
|
end
|
end
|
`NOP:
|
`NOP:
|
| Line 5693... |
Line 5755... |
begin
|
begin
|
if (fetchbuf0_pc==32'h0)
|
if (fetchbuf0_pc==32'h0)
|
$stop;
|
$stop;
|
if (fetchbuf0_pc==32'hF44)
|
if (fetchbuf0_pc==32'hF44)
|
$stop;
|
$stop;
|
if (fetchbuf0_pc==32'hFFFC2F71)
|
if (fetchbuf0_pc==32'hFFFC275A)
|
$stop;
|
$stop;
|
`ifdef SEGMENTATION
|
`ifdef SEGMENTATION
|
`ifdef SEGLIMITS
|
`ifdef SEGLIMITS
|
// If segment limit exceeded and not in the non-segmented area.
|
// If segment limit exceeded and not in the non-segmented area.
|
if (fetchbuf0_pc >= {sregs_lmt[3'd7],12'h000} && fetchbuf0_pc[ABW-1:ABW-4]!=4'hF)
|
if (fetchbuf0_pc >= {sregs_lmt[3'd7],12'h000} && fetchbuf0_pc[ABW-1:ABW-4]!=4'hF)
|
| Line 5927... |
Line 5989... |
begin
|
begin
|
if (fetchbuf1_pc==32'h0)
|
if (fetchbuf1_pc==32'h0)
|
$stop;
|
$stop;
|
if (fetchbuf1_pc==32'hF44)
|
if (fetchbuf1_pc==32'hF44)
|
$stop;
|
$stop;
|
if (fetchbuf1_pc==32'hFFFC2F71)
|
if (fetchbuf1_pc==32'hFFFC275A)
|
$stop;
|
$stop;
|
`ifdef SEGMENTATION
|
`ifdef SEGMENTATION
|
`ifdef SEGLIMITS
|
`ifdef SEGLIMITS
|
if (fetchbuf1_pc >= {sregs_lmt[3'd7],12'h000} && fetchbuf1_pc[ABW-1:ABW-4]!=4'hF)
|
if (fetchbuf1_pc >= {sregs_lmt[3'd7],12'h000} && fetchbuf1_pc[ABW-1:ABW-4]!=4'hF)
|
set_exception(tail,8'd244);
|
set_exception(tail,8'd244);
|
| Line 6097... |
Line 6159... |
input [2:0] tail;
|
input [2:0] tail;
|
begin
|
begin
|
iqentry_p_v [tail] <= rf_v [{1'b1,2'h0,Pn0}] || cond0 < 4'h2;
|
iqentry_p_v [tail] <= rf_v [{1'b1,2'h0,Pn0}] || cond0 < 4'h2;
|
iqentry_a1_v [tail] <= fnSource1_v( opcode0 ) | rf_v[ Ra0 ];
|
iqentry_a1_v [tail] <= fnSource1_v( opcode0 ) | rf_v[ Ra0 ];
|
iqentry_a2_v [tail] <= fnSource2_v( opcode0, fnFunc(fetchbuf0_instr)) | rf_v[Rb0];
|
iqentry_a2_v [tail] <= fnSource2_v( opcode0, fnFunc(fetchbuf0_instr)) | rf_v[Rb0];
|
iqentry_a3_v [tail] <= fnSource3_v( opcode0 ) | rf_v[ Rc0 ];
|
iqentry_a3_v [tail] <= fnSource3_v( opcode0, fnFunc(fetchbuf0_instr)) | rf_v[ Rc0 ];
|
iqentry_T_v [tail] <= fnSourceT_v( opcode0 ) | rf_v[ Rt0 ];
|
iqentry_T_v [tail] <= fnSourceT_v( opcode0, fnFunc(fetchbuf0_instr)) | rf_v[ Rt0 ];
|
if (fetchbuf0_rfw|fetchbuf0_pfw) begin
|
if (fetchbuf0_rfw|fetchbuf0_pfw) begin
|
$display("regv[%d] = %d", Rt0,rf_v[ Rt0 ]);
|
$display("regv[%d] = %d", Rt0,rf_v[ Rt0 ]);
|
rf_v[ Rt0 ] = fnRegIsAutoValid(Rt0);
|
rf_v[ Rt0 ] = fnRegIsAutoValid(Rt0);
|
$display("reg[%d] <= INV",Rt0);
|
$display("reg[%d] <= INV",Rt0);
|
rf_source[ Rt0 ] <= { fetchbuf0_mem, tail }; // top bit indicates ALU/MEM bus
|
rf_source[ Rt0 ] <= { fetchbuf0_mem, tail }; // top bit indicates ALU/MEM bus
|
| Line 6117... |
Line 6179... |
begin
|
begin
|
// The predicate is automatically valid for condiitions 0 and 1 (always false or always true).
|
// The predicate is automatically valid for condiitions 0 and 1 (always false or always true).
|
iqentry_p_v [tail] <= rf_v [{1'b1,2'h0,Pn1}] || cond1 < 4'h2;
|
iqentry_p_v [tail] <= rf_v [{1'b1,2'h0,Pn1}] || cond1 < 4'h2;
|
iqentry_a1_v [tail] <= fnSource1_v( opcode1 ) | rf_v[ Ra1 ];
|
iqentry_a1_v [tail] <= fnSource1_v( opcode1 ) | rf_v[ Ra1 ];
|
iqentry_a2_v [tail] <= fnSource2_v( opcode1, fnFunc(fetchbuf1_instr) ) | rf_v[ Rb1 ];
|
iqentry_a2_v [tail] <= fnSource2_v( opcode1, fnFunc(fetchbuf1_instr) ) | rf_v[ Rb1 ];
|
iqentry_a3_v [tail] <= fnSource3_v( opcode1 ) | rf_v[ Rc1 ];
|
iqentry_a3_v [tail] <= fnSource3_v( opcode1, fnFunc(fetchbuf1_instr)) | rf_v[ Rc1 ];
|
iqentry_T_v [tail] <= fnSourceT_v( opcode1 ) | rf_v[ Rt1 ];
|
iqentry_T_v [tail] <= fnSourceT_v( opcode1, fnFunc(fetchbuf1_instr)) | rf_v[ Rt1 ];
|
if (fetchbuf1_rfw|fetchbuf1_pfw) begin
|
if (fetchbuf1_rfw|fetchbuf1_pfw) begin
|
$display("1:regv[%d] = %d", Rt1,rf_v[ Rt1 ]);
|
$display("1:regv[%d] = %d", Rt1,rf_v[ Rt1 ]);
|
rf_v[ Rt1 ] = fnRegIsAutoValid(Rt1);
|
rf_v[ Rt1 ] = fnRegIsAutoValid(Rt1);
|
$display("reg[%d] <= INV",Rt1);
|
$display("reg[%d] <= INV",Rt1);
|
rf_source[ Rt1 ] <= { fetchbuf1_mem, tail }; // top bit indicates ALU/MEM bus
|
rf_source[ Rt1 ] <= { fetchbuf1_mem, tail }; // top bit indicates ALU/MEM bus
|
| Line 6208... |
Line 6270... |
//
|
//
|
// SOURCE 3 ... this is relatively straightforward, because all instructions
|
// SOURCE 3 ... this is relatively straightforward, because all instructions
|
// that have a source (i.e. every instruction but LUI) read from RC
|
// that have a source (i.e. every instruction but LUI) read from RC
|
//
|
//
|
// if the argument is an immediate or not needed, we're done
|
// if the argument is an immediate or not needed, we're done
|
if (fnSource3_v( opcode1 ) == `VAL) begin
|
if (fnSource3_v( opcode1,fnFunc(fetchbuf1_instr) ) == `VAL) begin
|
iqentry_a3_v [tail1] <= `VAL;
|
iqentry_a3_v [tail1] <= `VAL;
|
iqentry_a3_v [tail1] <= 4'hF;
|
iqentry_a3_v [tail1] <= 4'hF;
|
// iqentry_a1_s [tail1] <= 4'd0;
|
// iqentry_a1_s [tail1] <= 4'd0;
|
end
|
end
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
| Line 6236... |
Line 6298... |
//
|
//
|
// Target 3 ... this is relatively straightforward, because all instructions
|
// Target 3 ... this is relatively straightforward, because all instructions
|
// that have a source (i.e. every instruction but LUI) read from RC
|
// that have a source (i.e. every instruction but LUI) read from RC
|
//
|
//
|
// if the argument is an immediate or not needed, we're done
|
// if the argument is an immediate or not needed, we're done
|
if (fnSourceT_v( opcode1 ) == `VAL) begin
|
if (fnSourceT_v( opcode1,fnFunc(fetchbuf1_instr) ) == `VAL) begin
|
iqentry_T_v [tail1] <= `VAL;
|
iqentry_T_v [tail1] <= `VAL;
|
iqentry_T_v [tail1] <= 4'hF;
|
iqentry_T_v [tail1] <= 4'hF;
|
end
|
end
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
// if previous instruction writes nothing to RF, then get info from rf_v and rf_source
|
else if (!fetchbuf0_rfw) begin
|
else if (!fetchbuf0_rfw) begin
|
| Line 6413... |
Line 6475... |
input [2:0] tail;
|
input [2:0] tail;
|
input [6:0] Rt;
|
input [6:0] Rt;
|
input mem;
|
input mem;
|
begin
|
begin
|
if (Rt==7'h70) begin
|
if (Rt==7'h70) begin
|
rf_v[7'h40] <= `INV;
|
rf_v[7'h40] = `INV;
|
rf_v[7'h41] <= `INV;
|
rf_v[7'h41] = `INV;
|
rf_v[7'h42] <= `INV;
|
rf_v[7'h42] = `INV;
|
rf_v[7'h43] <= `INV;
|
rf_v[7'h43] = `INV;
|
rf_v[7'h44] <= `INV;
|
rf_v[7'h44] = `INV;
|
rf_v[7'h45] <= `INV;
|
rf_v[7'h45] = `INV;
|
rf_v[7'h46] <= `INV;
|
rf_v[7'h46] = `INV;
|
rf_v[7'h47] <= `INV;
|
rf_v[7'h47] = `INV;
|
rf_v[7'h48] <= `INV;
|
rf_v[7'h48] = `INV;
|
rf_v[7'h49] <= `INV;
|
rf_v[7'h49] = `INV;
|
rf_v[7'h4A] <= `INV;
|
rf_v[7'h4A] = `INV;
|
rf_v[7'h4B] <= `INV;
|
rf_v[7'h4B] = `INV;
|
rf_v[7'h4C] <= `INV;
|
rf_v[7'h4C] = `INV;
|
rf_v[7'h4D] <= `INV;
|
rf_v[7'h4D] = `INV;
|
rf_v[7'h4E] <= `INV;
|
rf_v[7'h4E] = `INV;
|
rf_v[7'h4F] <= `INV;
|
rf_v[7'h4F] = `INV;
|
rf_source[7'h40] <= { mem, tail };
|
rf_source[7'h40] <= { mem, tail };
|
rf_source[7'h41] <= { mem, tail };
|
rf_source[7'h41] <= { mem, tail };
|
rf_source[7'h42] <= { mem, tail };
|
rf_source[7'h42] <= { mem, tail };
|
rf_source[7'h43] <= { mem, tail };
|
rf_source[7'h43] <= { mem, tail };
|
rf_source[7'h44] <= { mem, tail };
|
rf_source[7'h44] <= { mem, tail };
|
