| Line 91... |
Line 91... |
// support for interrupts
|
// support for interrupts
|
// The instruction set is changed completely with many new instructions.
|
// The instruction set is changed completely with many new instructions.
|
// An instruction and data cache were added.
|
// An instruction and data cache were added.
|
// A WISHBONE bus interface was added,
|
// A WISHBONE bus interface was added,
|
//
|
//
|
// 52,635 (84,500 LC's)
|
// 53,950 (86,500 LC's)
|
// with segmentation
|
// with segmentation
|
// no bitfield, stack or FP ops
|
// no bitfield, stack or FP ops
|
//
|
//
|
// ============================================================================
|
// ============================================================================
|
//
|
//
|
| Line 104... |
Line 104... |
module Thor(corenum, rst_i, clk_i, clk_o, km, nmi_i, irq_i, vec_i, bte_o, cti_o, bl_o, lock_o, resv_o, resv_i, cres_o,
|
module Thor(corenum, rst_i, clk_i, clk_o, km, nmi_i, irq_i, vec_i, bte_o, cti_o, bl_o, lock_o, resv_o, resv_i, cres_o,
|
cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o);
|
cyc_o, stb_o, ack_i, err_i, we_o, sel_o, adr_o, dat_i, dat_o);
|
parameter DBW = 32; // databus width
|
parameter DBW = 32; // databus width
|
parameter ABW = 32; // address bus width
|
parameter ABW = 32; // address bus width
|
parameter RSTADDR = 64'hFFFFFFFFFFFFEFF0;
|
parameter RSTADDR = 64'hFFFFFFFFFFFFEFF0;
|
|
parameter STARTUP_POWER = 16'hFFFF;
|
localparam AMSB = ABW-1;
|
localparam AMSB = ABW-1;
|
parameter QENTRIES = 8;
|
parameter QENTRIES = 8;
|
parameter ALU1BIG = 0;
|
parameter ALU1BIG = 0;
|
parameter RESET1 = 4'd0;
|
parameter RESET1 = 4'd0;
|
parameter RESET2 = 4'd1;
|
parameter RESET2 = 4'd1;
|
| Line 226... |
Line 227... |
|
|
reg [3:0] rf_source [0:NREGS];
|
reg [3:0] rf_source [0:NREGS];
|
//reg [3:0] pf_source [15:0];
|
//reg [3:0] pf_source [15:0];
|
|
|
// instruction queue (ROB)
|
// instruction queue (ROB)
|
reg iq_cmt[0:7];
|
|
reg [7:0] iqentry_v; // entry valid? -- this should be the first bit
|
reg [7:0] iqentry_v; // entry valid? -- this should be the first bit
|
reg iqentry_out [0:7]; // instruction has been issued to an ALU ...
|
reg iqentry_out [0:7]; // instruction has been issued to an ALU ...
|
reg iqentry_done [0:7]; // instruction result valid
|
reg iqentry_done [0:7]; // instruction result valid
|
reg [7:0] iqentry_cmt; // commit result to machine state
|
reg [7:0] iqentry_cmt; // commit result to machine state
|
reg iqentry_bt [0:7]; // branch-taken (used only for branches)
|
reg iqentry_bt [0:7]; // branch-taken (used only for branches)
|
| Line 240... |
Line 240... |
reg iqentry_fp [0:7]; // is an floating point operation
|
reg iqentry_fp [0:7]; // is an floating point operation
|
reg iqentry_rfw [0:7]; // writes to register file
|
reg iqentry_rfw [0:7]; // writes to register file
|
reg [DBW-1:0] iqentry_res [0:7]; // instruction result
|
reg [DBW-1:0] iqentry_res [0:7]; // instruction result
|
reg [3:0] iqentry_insnsz [0:7]; // the size of the instruction
|
reg [3:0] iqentry_insnsz [0:7]; // the size of the instruction
|
reg [3:0] iqentry_cond [0:7]; // predicating condition
|
reg [3:0] iqentry_cond [0:7]; // predicating condition
|
|
reg [3:0] iqentry_preg [0:7]; // predicate regno
|
reg [3:0] iqentry_pred [0:7]; // predicate value
|
reg [3:0] iqentry_pred [0:7]; // predicate value
|
reg iqentry_p_v [0:7]; // predicate is valid
|
reg iqentry_p_v [0:7]; // predicate is valid
|
reg [3:0] iqentry_p_s [0:7]; // predicate source
|
reg [3:0] iqentry_p_s [0:7]; // predicate source
|
reg [7:0] iqentry_op [0:7]; // instruction opcode
|
reg [7:0] iqentry_op [0:7]; // instruction opcode
|
reg [5:0] iqentry_fn [0:7]; // instruction function
|
reg [5:0] iqentry_fn [0:7]; // instruction function
|
| Line 262... |
Line 263... |
reg [DBW-1:0] iqentry_T [0:7];
|
reg [DBW-1:0] iqentry_T [0:7];
|
reg iqentry_T_v [0:7];
|
reg iqentry_T_v [0:7];
|
reg [3:0] iqentry_T_s [0:7];
|
reg [3:0] iqentry_T_s [0:7];
|
reg [DBW-1:0] iqentry_pc [0:7]; // program counter for this instruction
|
reg [DBW-1:0] iqentry_pc [0:7]; // program counter for this instruction
|
|
|
wire iqentry_source [0:7];
|
reg [7:0] iqentry_source;
|
wire iqentry_imm [0:7];
|
wire iqentry_imm [0:7];
|
wire iqentry_memready [0:7];
|
wire iqentry_memready [0:7];
|
wire iqentry_memopsvalid [0:7];
|
wire iqentry_memopsvalid [0:7];
|
reg qstomp;
|
reg qstomp;
|
|
|
| Line 431... |
Line 432... |
wire [3:0] alu1_exc;
|
wire [3:0] alu1_exc;
|
reg alu1_v;
|
reg alu1_v;
|
wire alu1_branchmiss;
|
wire alu1_branchmiss;
|
reg [ABW+3:0] alu1_misspc;
|
reg [ABW+3:0] alu1_misspc;
|
|
|
wire mem_stringmiss;
|
wire mem_stringmissx;
|
|
reg mem_stringmiss;
|
wire branchmiss;
|
wire branchmiss;
|
wire [ABW+3:0] misspc;
|
wire [ABW+3:0] misspc;
|
|
|
`ifdef FLOATING_POINT
|
`ifdef FLOATING_POINT
|
reg fp0_ld;
|
reg fp0_ld;
|
| Line 480... |
Line 482... |
reg [7:0] dram0_op;
|
reg [7:0] dram0_op;
|
reg [5:0] dram0_fn;
|
reg [5:0] dram0_fn;
|
reg [8:0] dram0_tgt;
|
reg [8:0] dram0_tgt;
|
reg [3:0] dram0_id;
|
reg [3:0] dram0_id;
|
reg [3:0] dram0_exc;
|
reg [3:0] dram0_exc;
|
|
reg [ABW-1:0] dram0_misspc;
|
reg dram1_owns_bus;
|
reg dram1_owns_bus;
|
reg [DBW-1:0] dram1_data;
|
reg [DBW-1:0] dram1_data;
|
reg [DBW-1:0] dram1_datacmp;
|
reg [DBW-1:0] dram1_datacmp;
|
reg [DBW-1:0] dram1_addr;
|
reg [DBW-1:0] dram1_addr;
|
reg [7:0] dram1_op;
|
reg [7:0] dram1_op;
|
| Line 535... |
Line 538... |
wire [127:0] alu0_prod;
|
wire [127:0] alu0_prod;
|
wire alu0_mult_done;
|
wire alu0_mult_done;
|
wire [127:0] alu1_prod;
|
wire [127:0] alu1_prod;
|
wire alu1_mult_done;
|
wire alu1_mult_done;
|
|
|
|
reg exception_set;
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Debug
|
// Debug
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
|
|
wire [DBW-1:0] dbg_stat;
|
wire [DBW-1:0] dbg_stat1x;
|
|
reg [DBW-1:0] dbg_stat;
|
reg [DBW-1:0] dbg_ctrl;
|
reg [DBW-1:0] dbg_ctrl;
|
reg [ABW-1:0] dbg_adr0;
|
reg [ABW-1:0] dbg_adr0;
|
reg [ABW-1:0] dbg_adr1;
|
reg [ABW-1:0] dbg_adr1;
|
reg [ABW-1:0] dbg_adr2;
|
reg [ABW-1:0] dbg_adr2;
|
reg [ABW-1:0] dbg_adr3;
|
reg [ABW-1:0] dbg_adr3;
|
| Line 612... |
Line 618... |
|
|
wire dbg_stat0 = dbg_imatchA0 | dbg_imatchB0 | dbg_lmatch0 | dbg_smatch0;
|
wire dbg_stat0 = dbg_imatchA0 | dbg_imatchB0 | dbg_lmatch0 | dbg_smatch0;
|
wire dbg_stat1 = dbg_imatchA1 | dbg_imatchB1 | dbg_lmatch1 | dbg_smatch1;
|
wire dbg_stat1 = dbg_imatchA1 | dbg_imatchB1 | dbg_lmatch1 | dbg_smatch1;
|
wire dbg_stat2 = dbg_imatchA2 | dbg_imatchB2 | dbg_lmatch2 | dbg_smatch2;
|
wire dbg_stat2 = dbg_imatchA2 | dbg_imatchB2 | dbg_lmatch2 | dbg_smatch2;
|
wire dbg_stat3 = dbg_imatchA3 | dbg_imatchB3 | dbg_lmatch3 | dbg_smatch3;
|
wire dbg_stat3 = dbg_imatchA3 | dbg_imatchB3 | dbg_lmatch3 | dbg_smatch3;
|
assign dbg_stat = {dbg_stat3,dbg_stat2,dbg_stat1,dbg_stat0};
|
assign dbg_stat1x = {dbg_stat3,dbg_stat2,dbg_stat1,dbg_stat0};
|
|
|
|
|
reg [11:0] spr_bir;
|
reg [11:0] spr_bir;
|
|
|
//
|
//
|
// BRANCH-MISS LOGIC: livetarget
|
// BRANCH-MISS LOGIC: livetarget
|
//
|
//
|
// livetarget implies that there is a not-to-be-stomped instruction that targets the register in question
|
// livetarget implies that there is a not-to-be-stomped instruction that targets the register in question
|
// therefore, if it is zero it implies the rf_v value should become VALID on a branchmiss
|
// therefore, if it is zero it implies the rf_v value should become VALID on a branchmiss
|
//
|
//
|
|
/*
|
Thor_livetarget #(NREGS) ultgt1
|
Thor_livetarget #(NREGS) ultgt1
|
(
|
(
|
iqentry_v,
|
iqentry_v,
|
iqentry_stomp,
|
iqentry_stomp,
|
iqentry_cmt,
|
iqentry_cmt,
|
iqentry_tgt[0],
|
iqentry_tgt[0],
|
iqentry_tgt[1],
|
iqentry_tgt[1],
|
iqentry_tgt[2],
|
iqentry_tgt[2],
|
iqentry_tgt[3],
|
iqentry_tgt[3],
|
iqentry_tgt[4],
|
iqentry_tgt[4],
|
iqentry_tgt[5],
|
iqentry_tgt[5],
|
iqentry_tgt[6],
|
iqentry_tgt[6],
|
iqentry_tgt[7],
|
iqentry_tgt[7],
|
livetarget,
|
livetarget,
|
iqentry_0_livetarget,
|
iqentry_0_livetarget,
|
iqentry_1_livetarget,
|
iqentry_1_livetarget,
|
iqentry_2_livetarget,
|
iqentry_2_livetarget,
|
iqentry_3_livetarget,
|
iqentry_3_livetarget,
|
iqentry_4_livetarget,
|
iqentry_4_livetarget,
|
iqentry_5_livetarget,
|
iqentry_5_livetarget,
|
iqentry_6_livetarget,
|
iqentry_6_livetarget,
|
iqentry_7_livetarget
|
iqentry_7_livetarget
|
);
|
);
|
|
|
//
|
//
|
// BRANCH-MISS LOGIC: latestID
|
// BRANCH-MISS LOGIC: latestID
|
//
|
//
|
// latestID is the instruction queue ID of the newest instruction (latest) that targets
|
// latestID is the instruction queue ID of the newest instruction (latest) that targets
|
// a particular register. looks a lot like scheduling logic, but in reverse.
|
// a particular register. looks a lot like scheduling logic, but in reverse.
|
//
|
//
|
|
|
assign iqentry_0_latestID = ((missid == 3'd0)|| ((iqentry_0_livetarget & iqentry_1_cumulative) == {NREGS{1'b0}}))
|
assign iqentry_0_latestID = ((missid == 3'd0)|| ((iqentry_0_livetarget & iqentry_1_cumulative) == {NREGS{1'b0}}))
|
? iqentry_0_livetarget
|
? iqentry_0_livetarget
|
: {NREGS{1'b0}};
|
: {NREGS{1'b0}};
|
assign iqentry_0_cumulative = (missid == 3'd0)
|
assign iqentry_0_cumulative = (missid == 3'd0)
|
? iqentry_0_livetarget
|
? iqentry_0_livetarget
|
: iqentry_0_livetarget | iqentry_1_cumulative;
|
: iqentry_0_livetarget | iqentry_1_cumulative;
|
|
|
assign iqentry_1_latestID = ((missid == 3'd1)|| ((iqentry_1_livetarget & iqentry_2_cumulative) == {NREGS{1'b0}}))
|
assign iqentry_1_latestID = ((missid == 3'd1)|| ((iqentry_1_livetarget & iqentry_2_cumulative) == {NREGS{1'b0}}))
|
? iqentry_1_livetarget
|
? iqentry_1_livetarget
|
: {NREGS{1'b0}};
|
: {NREGS{1'b0}};
|
assign iqentry_1_cumulative = (missid == 3'd1)
|
assign iqentry_1_cumulative = (missid == 3'd1)
|
? iqentry_1_livetarget
|
? iqentry_1_livetarget
|
: iqentry_1_livetarget | iqentry_2_cumulative;
|
: iqentry_1_livetarget | iqentry_2_cumulative;
|
|
|
assign iqentry_2_latestID = ((missid == 3'd2) || ((iqentry_2_livetarget & iqentry_3_cumulative) == {NREGS{1'b0}}))
|
assign iqentry_2_latestID = ((missid == 3'd2) || ((iqentry_2_livetarget & iqentry_3_cumulative) == {NREGS{1'b0}}))
|
? iqentry_2_livetarget
|
? iqentry_2_livetarget
|
: {NREGS{1'b0}};
|
: {NREGS{1'b0}};
|
assign iqentry_2_cumulative = (missid == 3'd2)
|
assign iqentry_2_cumulative = (missid == 3'd2)
|
? iqentry_2_livetarget
|
? iqentry_2_livetarget
|
: iqentry_2_livetarget | iqentry_3_cumulative;
|
: iqentry_2_livetarget | iqentry_3_cumulative;
|
|
|
assign iqentry_3_latestID = ((missid == 3'd3)|| ((iqentry_3_livetarget & iqentry_4_cumulative) == {NREGS{1'b0}}))
|
assign iqentry_3_latestID = ((missid == 3'd3)|| ((iqentry_3_livetarget & iqentry_4_cumulative) == {NREGS{1'b0}}))
|
? iqentry_3_livetarget
|
? iqentry_3_livetarget
|
: {NREGS{1'b0}};
|
: {NREGS{1'b0}};
|
assign iqentry_3_cumulative = (missid == 3'd3)
|
assign iqentry_3_cumulative = (missid == 3'd3)
|
? iqentry_3_livetarget
|
? iqentry_3_livetarget
|
: iqentry_3_livetarget | iqentry_4_cumulative;
|
: iqentry_3_livetarget | iqentry_4_cumulative;
|
|
|
assign iqentry_4_latestID = ((missid == 3'd4) || ((iqentry_4_livetarget & iqentry_5_cumulative) == {NREGS{1'b0}}))
|
assign iqentry_4_latestID = ((missid == 3'd4) || ((iqentry_4_livetarget & iqentry_5_cumulative) == {NREGS{1'b0}}))
|
? iqentry_4_livetarget
|
? iqentry_4_livetarget
|
: {NREGS{1'b0}};
|
: {NREGS{1'b0}};
|
assign iqentry_4_cumulative = (missid == 3'd4)
|
assign iqentry_4_cumulative = (missid == 3'd4)
|
? iqentry_4_livetarget
|
? iqentry_4_livetarget
|
: iqentry_4_livetarget | iqentry_5_cumulative;
|
: iqentry_4_livetarget | iqentry_5_cumulative;
|
|
|
assign iqentry_5_latestID = ((missid == 3'd5)|| ((iqentry_5_livetarget & iqentry_6_cumulative) == {NREGS{1'b0}}))
|
assign iqentry_5_latestID = ((missid == 3'd5)|| ((iqentry_5_livetarget & iqentry_6_cumulative) == {NREGS{1'b0}}))
|
? iqentry_5_livetarget
|
? iqentry_5_livetarget
|
: 287'd0;
|
: 287'd0;
|
assign iqentry_5_cumulative = (missid == 3'd5)
|
assign iqentry_5_cumulative = (missid == 3'd5)
|
? iqentry_5_livetarget
|
? iqentry_5_livetarget
|
: iqentry_5_livetarget | iqentry_6_cumulative;
|
: iqentry_5_livetarget | iqentry_6_cumulative;
|
|
|
assign iqentry_6_latestID = ((missid == 3'd6) || ((iqentry_6_livetarget & iqentry_7_cumulative) == {NREGS{1'b0}}))
|
assign iqentry_6_latestID = ((missid == 3'd6) || ((iqentry_6_livetarget & iqentry_7_cumulative) == {NREGS{1'b0}}))
|
? iqentry_6_livetarget
|
? iqentry_6_livetarget
|
: {NREGS{1'b0}};
|
: {NREGS{1'b0}};
|
assign iqentry_6_cumulative = (missid == 3'd6)
|
assign iqentry_6_cumulative = (missid == 3'd6)
|
? iqentry_6_livetarget
|
? iqentry_6_livetarget
|
: iqentry_6_livetarget | iqentry_7_cumulative;
|
: iqentry_6_livetarget | iqentry_7_cumulative;
|
|
|
assign iqentry_7_latestID = ((missid == 3'd7) || ((iqentry_7_livetarget & iqentry_0_cumulative) == {NREGS{1'b0}}))
|
assign iqentry_7_latestID = ((missid == 3'd7) || ((iqentry_7_livetarget & iqentry_0_cumulative) == {NREGS{1'b0}}))
|
? iqentry_7_livetarget
|
? iqentry_7_livetarget
|
: {NREGS{1'b0}};
|
: {NREGS{1'b0}};
|
assign iqentry_7_cumulative = (missid==3'd7)
|
assign iqentry_7_cumulative = (missid==3'd7)
|
? iqentry_7_livetarget
|
? iqentry_7_livetarget
|
: iqentry_7_livetarget | iqentry_0_cumulative;
|
: iqentry_7_livetarget | iqentry_0_cumulative;
|
|
|
assign
|
|
iqentry_source[0] = | iqentry_0_latestID,
|
|
iqentry_source[1] = | iqentry_1_latestID,
|
|
iqentry_source[2] = | iqentry_2_latestID,
|
|
iqentry_source[3] = | iqentry_3_latestID,
|
|
iqentry_source[4] = | iqentry_4_latestID,
|
|
iqentry_source[5] = | iqentry_5_latestID,
|
|
iqentry_source[6] = | iqentry_6_latestID,
|
|
iqentry_source[7] = | iqentry_7_latestID;
|
|
|
|
|
assign
|
|
iqentry_source[0] = | iqentry_0_latestID,
|
|
iqentry_source[1] = | iqentry_1_latestID,
|
|
iqentry_source[2] = | iqentry_2_latestID,
|
|
iqentry_source[3] = | iqentry_3_latestID,
|
|
iqentry_source[4] = | iqentry_4_latestID,
|
|
iqentry_source[5] = | iqentry_5_latestID,
|
|
iqentry_source[6] = | iqentry_6_latestID,
|
|
iqentry_source[7] = | iqentry_7_latestID;
|
|
*/
|
|
always @*
|
|
begin
|
|
iqentry_source = 8'h00;
|
|
if (missid==head0) begin
|
|
if (iqentry_v[head0] && !iqentry_stomp[head0])
|
|
iqentry_source[head0] = !fnRegIsAutoValid(iqentry_tgt[head0]);
|
|
end
|
|
else if (missid==head1) begin
|
|
if (iqentry_v[head0] && !iqentry_stomp[head0])
|
|
iqentry_source[head0] = !fnRegIsAutoValid(iqentry_tgt[head0]);
|
|
if (iqentry_v[head1] && !iqentry_stomp[head1])
|
|
iqentry_source[head1] = !fnRegIsAutoValid(iqentry_tgt[head1]);
|
|
end
|
|
else if (missid==head2) begin
|
|
if (iqentry_v[head0] && !iqentry_stomp[head0])
|
|
iqentry_source[head0] = !fnRegIsAutoValid(iqentry_tgt[head0]);
|
|
if (iqentry_v[head1] && !iqentry_stomp[head1])
|
|
iqentry_source[head1] = !fnRegIsAutoValid(iqentry_tgt[head1]);
|
|
if (iqentry_v[head2] && !iqentry_stomp[head2])
|
|
iqentry_source[head2] = !fnRegIsAutoValid(iqentry_tgt[head2]);
|
|
end
|
|
else if (missid==head3) begin
|
|
if (iqentry_v[head0] && !iqentry_stomp[head0])
|
|
iqentry_source[head0] = !fnRegIsAutoValid(iqentry_tgt[head0]);
|
|
if (iqentry_v[head1] && !iqentry_stomp[head1])
|
|
iqentry_source[head1] = !fnRegIsAutoValid(iqentry_tgt[head1]);
|
|
if (iqentry_v[head2] && !iqentry_stomp[head2])
|
|
iqentry_source[head2] = !fnRegIsAutoValid(iqentry_tgt[head2]);
|
|
if (iqentry_v[head3] && !iqentry_stomp[head3])
|
|
iqentry_source[head3] = !fnRegIsAutoValid(iqentry_tgt[head3]);
|
|
end
|
|
else if (missid==head4) begin
|
|
if (iqentry_v[head0] && !iqentry_stomp[head0])
|
|
iqentry_source[head0] = !fnRegIsAutoValid(iqentry_tgt[head0]);
|
|
if (iqentry_v[head1] && !iqentry_stomp[head1])
|
|
iqentry_source[head1] = !fnRegIsAutoValid(iqentry_tgt[head1]);
|
|
if (iqentry_v[head2] && !iqentry_stomp[head2])
|
|
iqentry_source[head2] = !fnRegIsAutoValid(iqentry_tgt[head2]);
|
|
if (iqentry_v[head3] && !iqentry_stomp[head3])
|
|
iqentry_source[head3] = !fnRegIsAutoValid(iqentry_tgt[head3]);
|
|
if (iqentry_v[head4] && !iqentry_stomp[head4])
|
|
iqentry_source[head4] = !fnRegIsAutoValid(iqentry_tgt[head4]);
|
|
end
|
|
else if (missid==head5) begin
|
|
if (iqentry_v[head0] && !iqentry_stomp[head0])
|
|
iqentry_source[head0] = !fnRegIsAutoValid(iqentry_tgt[head0]);
|
|
if (iqentry_v[head1] && !iqentry_stomp[head1])
|
|
iqentry_source[head1] = !fnRegIsAutoValid(iqentry_tgt[head1]);
|
|
if (iqentry_v[head2] && !iqentry_stomp[head2])
|
|
iqentry_source[head2] = !fnRegIsAutoValid(iqentry_tgt[head2]);
|
|
if (iqentry_v[head3] && !iqentry_stomp[head3])
|
|
iqentry_source[head3] = !fnRegIsAutoValid(iqentry_tgt[head3]);
|
|
if (iqentry_v[head4] && !iqentry_stomp[head4])
|
|
iqentry_source[head4] = !fnRegIsAutoValid(iqentry_tgt[head4]);
|
|
if (iqentry_v[head5] && !iqentry_stomp[head5])
|
|
iqentry_source[head5] = !fnRegIsAutoValid(iqentry_tgt[head5]);
|
|
end
|
|
else if (missid==head6) begin
|
|
if (iqentry_v[head0] && !iqentry_stomp[head0])
|
|
iqentry_source[head0] = !fnRegIsAutoValid(iqentry_tgt[head0]);
|
|
if (iqentry_v[head1] && !iqentry_stomp[head1])
|
|
iqentry_source[head1] = !fnRegIsAutoValid(iqentry_tgt[head1]);
|
|
if (iqentry_v[head2] && !iqentry_stomp[head2])
|
|
iqentry_source[head2] = !fnRegIsAutoValid(iqentry_tgt[head2]);
|
|
if (iqentry_v[head3] && !iqentry_stomp[head3])
|
|
iqentry_source[head3] = !fnRegIsAutoValid(iqentry_tgt[head3]);
|
|
if (iqentry_v[head4] && !iqentry_stomp[head4])
|
|
iqentry_source[head4] = !fnRegIsAutoValid(iqentry_tgt[head4]);
|
|
if (iqentry_v[head5] && !iqentry_stomp[head5])
|
|
iqentry_source[head5] = !fnRegIsAutoValid(iqentry_tgt[head5]);
|
|
if (iqentry_v[head6] && !iqentry_stomp[head6])
|
|
iqentry_source[head6] = !fnRegIsAutoValid(iqentry_tgt[head6]);
|
|
end
|
|
else if (missid==head7) begin
|
|
if (iqentry_v[head0] && !iqentry_stomp[head0])
|
|
iqentry_source[head0] = !fnRegIsAutoValid(iqentry_tgt[head0]);
|
|
if (iqentry_v[head1] && !iqentry_stomp[head1])
|
|
iqentry_source[head1] = !fnRegIsAutoValid(iqentry_tgt[head1]);
|
|
if (iqentry_v[head2] && !iqentry_stomp[head2])
|
|
iqentry_source[head2] = !fnRegIsAutoValid(iqentry_tgt[head2]);
|
|
if (iqentry_v[head3] && !iqentry_stomp[head3])
|
|
iqentry_source[head3] = !fnRegIsAutoValid(iqentry_tgt[head3]);
|
|
if (iqentry_v[head4] && !iqentry_stomp[head4])
|
|
iqentry_source[head4] = !fnRegIsAutoValid(iqentry_tgt[head4]);
|
|
if (iqentry_v[head5] && !iqentry_stomp[head5])
|
|
iqentry_source[head5] = !fnRegIsAutoValid(iqentry_tgt[head5]);
|
|
if (iqentry_v[head6] && !iqentry_stomp[head6])
|
|
iqentry_source[head6] = !fnRegIsAutoValid(iqentry_tgt[head6]);
|
|
if (iqentry_v[head7] && !iqentry_stomp[head7])
|
|
iqentry_source[head7] = !fnRegIsAutoValid(iqentry_tgt[head7]);
|
|
end
|
|
end
|
|
|
//assign iqentry_0_islot = iqentry_islot[0];
|
//assign iqentry_0_islot = iqentry_islot[0];
|
//assign iqentry_1_islot = iqentry_islot[1];
|
//assign iqentry_1_islot = iqentry_islot[1];
|
//assign iqentry_2_islot = iqentry_islot[2];
|
//assign iqentry_2_islot = iqentry_islot[2];
|
//assign iqentry_3_islot = iqentry_islot[3];
|
//assign iqentry_3_islot = iqentry_islot[3];
|
| Line 834... |
Line 932... |
wire [3:0] Pt0 = fetchbuf0_instr[11:8];
|
wire [3:0] Pt0 = fetchbuf0_instr[11:8];
|
wire [3:0] Pn1 = fetchbuf1_instr[7:4];
|
wire [3:0] Pn1 = fetchbuf1_instr[7:4];
|
wire [3:0] Pt1 = fetchbuf1_instr[11:8];
|
wire [3:0] Pt1 = fetchbuf1_instr[11:8];
|
|
|
function [6:0] fnRa;
|
function [6:0] fnRa;
|
input [63:0] insn;
|
input [63:0] isn;
|
case(insn[7:0])
|
case(isn[7:0])
|
8'h11: fnRa = 7'h51; // RTS short form
|
8'h11: fnRa = 7'h51; // RTS short form
|
default:
|
default:
|
case(insn[15:8])
|
case(isn[15:8])
|
`RTI: fnRa = 7'h5E;
|
`RTI: fnRa = 7'h5E;
|
`RTD: fnRa = 7'h5B;
|
`RTD: fnRa = 7'h5B;
|
`RTE: fnRa = 7'h5D;
|
`RTE: fnRa = 7'h5D;
|
`JSR,`JSRS,`JSRZ,`SYS,`INT,`RTS,`RTS2:
|
`JSR,`JSRS,`JSRZ,`SYS,`INT,`RTS,`RTS2:
|
fnRa = {3'h5,insn[23:20]};
|
fnRa = {3'h5,isn[23:20]};
|
`TLB: fnRa = {1'b0,insn[29:24]};
|
`TLB: fnRa = {1'b0,isn[29:24]};
|
`P: fnRa = 7'h70;
|
`P: fnRa = 7'h70;
|
// `PUSH,`PEA,`POP,`LINK: fnRa = 7'd27;
|
`LOOP: fnRa = 7'h5F;
|
default: fnRa = {1'b0,insn[`INSTRUCTION_RA]};
|
`ifdef STACKOPS
|
|
`PUSH,`PEA,`POP,`LINK: fnRa = 7'd27;
|
|
`endif
|
|
default: fnRa = {1'b0,isn[`INSTRUCTION_RA]};
|
endcase
|
endcase
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [6:0] fnRb;
|
function [6:0] fnRb;
|
input [63:0] insn;
|
input [63:0] isn;
|
if (insn[7:0]==8'h11) // RTS short form
|
if (isn[7:0]==8'h11) // RTS short form
|
fnRb = 7'h51;
|
fnRb = 7'h51;
|
else
|
else
|
case(insn[15:8])
|
case(isn[15:8])
|
`RTI: fnRb = 7'h5E;
|
`RTI: fnRb = 7'h5E;
|
`RTD: fnRb = 7'h5B;
|
`RTD: fnRb = 7'h5B;
|
`RTE: fnRb = 7'h5D;
|
`RTE: fnRb = 7'h5D;
|
`RTS2: fnRb = 7'd27;
|
`RTS2: fnRb = 7'd27;
|
`RTS,`STP,`TLB,`POP: fnRb = 7'd0;
|
|
`LOOP: fnRb = 7'h73;
|
`LOOP: fnRb = 7'h73;
|
|
`RTS,`STP,`TLB,`POP: fnRb = 7'd0;
|
`JSR,`JSRS,`JSRZ,`SYS,`INT:
|
`JSR,`JSRS,`JSRZ,`SYS,`INT:
|
fnRb = {3'h5,insn[23:20]};
|
fnRb = {3'h5,isn[23:20]};
|
`SWS: fnRb = {1'b1,insn[27:22]};
|
`SWS: fnRb = {1'b1,isn[27:22]};
|
`ifdef STACKOPS
|
`ifdef STACKOPS
|
`PUSH: fnRb = insn[22:16];
|
`PUSH: fnRb = isn[22:16];
|
`LINK: fnRb = {1'b0,insn[27:22]};
|
`LINK: fnRb = {1'b0,isn[27:22]};
|
`PEA: fnRb = {1'b0,insn[21:16]};
|
`PEA: fnRb = {1'b0,isn[21:16]};
|
`endif
|
`endif
|
default: fnRb = {1'b0,insn[`INSTRUCTION_RB]};
|
default: fnRb = {1'b0,isn[`INSTRUCTION_RB]};
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [6:0] fnRc;
|
function [6:0] fnRc;
|
input [63:0] insn;
|
input [63:0] isn;
|
fnRc = {1'b0,insn[`INSTRUCTION_RC]};
|
fnRc = {1'b0,isn[`INSTRUCTION_RC]};
|
endfunction
|
endfunction
|
|
|
function [3:0] fnCar;
|
function [3:0] fnCar;
|
input [63:0] insn;
|
input [63:0] isn;
|
if (insn[7:0]==8'h11) // RTS short form
|
if (isn[7:0]==8'h11) // RTS short form
|
fnCar = 4'h1;
|
fnCar = 4'h1;
|
else
|
else
|
case(insn[15:8])
|
case(isn[15:8])
|
`RTI: fnCar = 4'hE;
|
`RTI: fnCar = 4'hE;
|
`RTD: fnCar = 4'hB;
|
`RTD: fnCar = 4'hB;
|
`RTE: fnCar = 4'hD;
|
`RTE: fnCar = 4'hD;
|
`JSR,`JSRS,`JSRZ,`SYS,`INT,`RTS,`RTS2:
|
`JSR,`JSRS,`JSRZ,`SYS,`INT,`RTS,`RTS2:
|
fnCar = {insn[23:20]};
|
fnCar = {isn[23:20]};
|
default: fnCar = 4'h0;
|
default: fnCar = 4'h0;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [5:0] fnFunc;
|
function [5:0] fnFunc;
|
input [63:0] insn;
|
input [63:0] isn;
|
if (insn[7:0]==8'h11) // RTS short form
|
if (isn[7:0]==8'h11) // RTS short form
|
fnFunc = 6'h00; // func is used as a small immediate
|
fnFunc = 6'h00; // func is used as a small immediate
|
else
|
else
|
casex(insn[15:8])
|
case(isn[15:8])
|
`BITFIELD: fnFunc = insn[43:40];
|
`BITFIELD: fnFunc = isn[43:40];
|
`CMP: fnFunc = insn[31:28];
|
8'h10: fnFunc = isn[31:28];
|
`TST: fnFunc = insn[23:22];
|
8'h11: fnFunc = isn[31:28];
|
`INC: fnFunc = insn[24:22];
|
8'h12: fnFunc = isn[31:28];
|
`RTS,`RTS2: fnFunc = insn[19:16]; // used to pass a small immediate
|
8'h13: fnFunc = isn[31:28];
|
`CACHE: fnFunc = insn[31:26];
|
8'h14: fnFunc = isn[31:28];
|
|
8'h15: fnFunc = isn[31:28];
|
|
8'h16: fnFunc = isn[31:28];
|
|
8'h17: fnFunc = isn[31:28];
|
|
8'h18: fnFunc = isn[31:28];
|
|
8'h19: fnFunc = isn[31:28];
|
|
8'h1A: fnFunc = isn[31:28];
|
|
8'h1B: fnFunc = isn[31:28];
|
|
8'h1C: fnFunc = isn[31:28];
|
|
8'h1D: fnFunc = isn[31:28];
|
|
8'h1E: fnFunc = isn[31:28];
|
|
8'h1F: fnFunc = isn[31:28];
|
|
8'h00: fnFunc = isn[23:22];
|
|
8'h01: fnFunc = isn[23:22];
|
|
8'h02: fnFunc = isn[23:22];
|
|
8'h03: fnFunc = isn[23:22];
|
|
8'h04: fnFunc = isn[23:22];
|
|
8'h05: fnFunc = isn[23:22];
|
|
8'h06: fnFunc = isn[23:22];
|
|
8'h07: fnFunc = isn[23:22];
|
|
8'h08: fnFunc = isn[23:22];
|
|
8'h09: fnFunc = isn[23:22];
|
|
8'h0A: fnFunc = isn[23:22];
|
|
8'h0B: fnFunc = isn[23:22];
|
|
8'h0C: fnFunc = isn[23:22];
|
|
8'h0D: fnFunc = isn[23:22];
|
|
8'h0E: fnFunc = isn[23:22];
|
|
8'h0F: fnFunc = isn[23:22];
|
|
`INC: fnFunc = isn[24:22];
|
|
`RTS,`RTS2: fnFunc = isn[19:16]; // used to pass a small immediate
|
|
`CACHE: fnFunc = isn[31:26];
|
default:
|
default:
|
fnFunc = insn[39:34];
|
fnFunc = isn[39:34];
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
// Returns true if the operation is limited to ALU #0
|
// Returns true if the operation is limited to ALU #0
|
function fnIsAlu0Op;
|
function fnIsAlu0Op;
|
| Line 987... |
Line 1118... |
//
|
//
|
// 1 if the the operand is automatically valid,
|
// 1 if the the operand is automatically valid,
|
// 0 if we need a RF value
|
// 0 if we need a RF value
|
function fnSource1_v;
|
function fnSource1_v;
|
input [7:0] opcode;
|
input [7:0] opcode;
|
casex(opcode)
|
case(opcode)
|
`SEI,`CLI,`MEMSB,`MEMDB,`SYNC,`NOP,`STP:
|
`SEI,`CLI,`MEMSB,`MEMDB,`SYNC,`NOP,`STP:
|
fnSource1_v = 1'b1;
|
fnSource1_v = 1'b1;
|
`BR,`LOOP: fnSource1_v = 1'b1;
|
|
`LDI,`LDIS,`IMM: fnSource1_v = 1'b1;
|
`LDI,`LDIS,`IMM: fnSource1_v = 1'b1;
|
|
default:
|
|
case(opcode[7:4])
|
|
`BR: fnSource1_v = 1'b1;
|
default: fnSource1_v = 1'b0;
|
default: fnSource1_v = 1'b0;
|
endcase
|
endcase
|
|
endcase
|
endfunction
|
endfunction
|
|
|
//
|
//
|
// 1 if the the operand is automatically valid,
|
// 1 if the the operand is automatically valid,
|
// 0 if we need a RF value
|
// 0 if we need a RF value
|
function fnSource2_v;
|
function fnSource2_v;
|
input [7:0] opcode;
|
input [7:0] opcode;
|
input [5:0] func;
|
input [5:0] func;
|
casex(opcode)
|
case(opcode)
|
`R,`P: fnSource2_v = 1'b1;
|
`R,`P: fnSource2_v = 1'b1;
|
`LDI,`STI,`LDIS,`IMM,`NOP,`STP: fnSource2_v = 1'b1;
|
`LDI,`LDIS,`IMM,`NOP,`STP: fnSource2_v = 1'b1;
|
`SEI,`CLI,`MEMSB,`MEMDB,`SYNC:
|
`SEI,`CLI,`MEMSB,`MEMDB,`SYNC:
|
fnSource2_v = 1'b1;
|
fnSource2_v = 1'b1;
|
`RTI,`RTD,`RTE: fnSource2_v = 1'b1;
|
`RTI,`RTD,`RTE: fnSource2_v = 1'b1;
|
`TST: fnSource2_v = 1'b1;
|
// TST
|
|
8'h00: fnSource2_v = 1'b1;
|
|
8'h01: fnSource2_v = 1'b1;
|
|
8'h02: fnSource2_v = 1'b1;
|
|
8'h03: fnSource2_v = 1'b1;
|
|
8'h04: fnSource2_v = 1'b1;
|
|
8'h05: fnSource2_v = 1'b1;
|
|
8'h06: fnSource2_v = 1'b1;
|
|
8'h07: fnSource2_v = 1'b1;
|
|
8'h08: fnSource2_v = 1'b1;
|
|
8'h09: fnSource2_v = 1'b1;
|
|
8'h0A: fnSource2_v = 1'b1;
|
|
8'h0B: fnSource2_v = 1'b1;
|
|
8'h0C: fnSource2_v = 1'b1;
|
|
8'h0D: fnSource2_v = 1'b1;
|
|
8'h0E: fnSource2_v = 1'b1;
|
|
8'h0F: fnSource2_v = 1'b1;
|
`ADDI,`ADDUI,`ADDUIS:
|
`ADDI,`ADDUI,`ADDUIS:
|
fnSource2_v = 1'b1;
|
fnSource2_v = 1'b1;
|
`_2ADDUI,`_4ADDUI,`_8ADDUI,`_16ADDUI:
|
`_2ADDUI,`_4ADDUI,`_8ADDUI,`_16ADDUI:
|
fnSource2_v = 1'b1;
|
fnSource2_v = 1'b1;
|
`SUBI,`SUBUI: fnSource2_v = 1'b1;
|
`SUBI,`SUBUI: fnSource2_v = 1'b1;
|
`CMPI: fnSource2_v = 1'b1;
|
// CMPI
|
|
8'h20: fnSource2_v = 1'b1;
|
|
8'h21: fnSource2_v = 1'b1;
|
|
8'h22: fnSource2_v = 1'b1;
|
|
8'h23: fnSource2_v = 1'b1;
|
|
8'h24: fnSource2_v = 1'b1;
|
|
8'h25: fnSource2_v = 1'b1;
|
|
8'h26: fnSource2_v = 1'b1;
|
|
8'h27: fnSource2_v = 1'b1;
|
|
8'h28: fnSource2_v = 1'b1;
|
|
8'h29: fnSource2_v = 1'b1;
|
|
8'h2A: fnSource2_v = 1'b1;
|
|
8'h2B: fnSource2_v = 1'b1;
|
|
8'h2C: fnSource2_v = 1'b1;
|
|
8'h2D: fnSource2_v = 1'b1;
|
|
8'h2E: fnSource2_v = 1'b1;
|
|
8'h2F: fnSource2_v = 1'b1;
|
|
// BR
|
|
8'h30: fnSource2_v = 1'b1;
|
|
8'h31: fnSource2_v = 1'b1;
|
|
8'h32: fnSource2_v = 1'b1;
|
|
8'h33: fnSource2_v = 1'b1;
|
|
8'h34: fnSource2_v = 1'b1;
|
|
8'h35: fnSource2_v = 1'b1;
|
|
8'h36: fnSource2_v = 1'b1;
|
|
8'h37: fnSource2_v = 1'b1;
|
|
8'h38: fnSource2_v = 1'b1;
|
|
8'h39: fnSource2_v = 1'b1;
|
|
8'h3A: fnSource2_v = 1'b1;
|
|
8'h3B: fnSource2_v = 1'b1;
|
|
8'h3C: fnSource2_v = 1'b1;
|
|
8'h3D: fnSource2_v = 1'b1;
|
|
8'h3E: fnSource2_v = 1'b1;
|
|
8'h3F: fnSource2_v = 1'b1;
|
`MULI,`MULUI,`DIVI,`DIVUI:
|
`MULI,`MULUI,`DIVI,`DIVUI:
|
fnSource2_v = 1'b1;
|
fnSource2_v = 1'b1;
|
`ANDI,`BITI: fnSource2_v = 1'b1;
|
`ANDI,`BITI: fnSource2_v = 1'b1;
|
`ORI: fnSource2_v = 1'b1;
|
`ORI: fnSource2_v = 1'b1;
|
`EORI: fnSource2_v = 1'b1;
|
`EORI: fnSource2_v = 1'b1;
|
| Line 1029... |
Line 1212... |
fnSource2_v = `FALSE;
|
fnSource2_v = `FALSE;
|
`CACHE,`LCL,`TLB,
|
`CACHE,`LCL,`TLB,
|
`LVB,`LVC,`LVH,`LVW,`LVWAR,
|
`LVB,`LVC,`LVH,`LVW,`LVWAR,
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWS,`LEA,`STI,`INC:
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWS,`LEA,`STI,`INC:
|
fnSource2_v = 1'b1;
|
fnSource2_v = 1'b1;
|
`JSR,`JSRS,`JSRZ,`SYS,`INT,`RTS,`BR:
|
`JSR,`JSRS,`JSRZ,`SYS,`INT,`RTS:
|
fnSource2_v = 1'b1;
|
fnSource2_v = 1'b1;
|
`MTSPR,`MFSPR,`POP,`UNLINK:
|
`MTSPR,`MFSPR,`POP,`UNLINK:
|
fnSource2_v = 1'b1;
|
fnSource2_v = 1'b1;
|
// `BFSET,`BFCLR,`BFCHG,`BFEXT,`BFEXTU: // but not BFINS
|
`BITFIELD:
|
// fnSource2_v = 1'b1;
|
if (func==`BFINS)
|
|
fnSource2_v = 1'b0;
|
|
else
|
|
fnSource2_v = 1'b1;
|
|
`LOOP: fnSource2_v = 1'b0;
|
default: fnSource2_v = 1'b0;
|
default: fnSource2_v = 1'b0;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
|
|
| Line 1047... |
Line 1234... |
// a valid status.
|
// a valid status.
|
// 1 if the the operand is automatically valid,
|
// 1 if the the operand is automatically valid,
|
// 0 if we need a RF value
|
// 0 if we need a RF value
|
function fnSource3_v;
|
function fnSource3_v;
|
input [7:0] opcode;
|
input [7:0] opcode;
|
casex(opcode)
|
case(opcode)
|
`SBX,`SCX,`SHX,`SWX,`CAS,`STMV,`STCMP,`STFND: fnSource3_v = 1'b0;
|
`SBX,`SCX,`SHX,`SWX,`CAS,`STMV,`STCMP,`STFND: fnSource3_v = 1'b0;
|
`MUX: fnSource3_v = 1'b0;
|
`MUX: fnSource3_v = 1'b0;
|
default: fnSource3_v = 1'b1;
|
default: fnSource3_v = 1'b1;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function fnSourceT_v;
|
function fnSourceT_v;
|
input [7:0] opcode;
|
input [7:0] opcode;
|
casex(opcode)
|
case(opcode)
|
`BR,
|
// BR
|
|
8'h30,8'h31,8'h32,8'h33,
|
|
8'h34,8'h35,8'h36,8'h37,
|
|
8'h38,8'h39,8'h3A,8'h3B,
|
|
8'h3C,8'h3D,8'h3E,8'h3F,
|
`SB,`SC,`SH,`SW,`SBX,`SCX,`SHX,`SWX,`SWS,
|
`SB,`SC,`SH,`SW,`SBX,`SCX,`SHX,`SWX,`SWS,
|
`CACHE,
|
`CACHE,
|
`SEI,`CLI,`NOP,`STP,
|
`SEI,`CLI,`NOP,`STP,`RTI,`RTD,`RTE,
|
`MEMSB,`MEMDB,`SYNC:
|
`MEMSB,`MEMDB,`SYNC:
|
fnSourceT_v = 1'b1;
|
fnSourceT_v = 1'b1;
|
default: fnSourceT_v = 1'b0;
|
default: fnSourceT_v = 1'b0;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
// Return the number of register read ports required for an instruction.
|
// Return the number of register read ports required for an instruction.
|
function [2:0] fnNumReadPorts;
|
function [2:0] fnNumReadPorts;
|
input [63:0] ins;
|
input [63:0] ins;
|
casex(fnOpcode(ins))
|
case(fnOpcode(ins))
|
`SEI,`CLI,`MEMSB,`MEMDB,`SYNC,`NOP,`MOVS,`STP:
|
`SEI,`CLI,`MEMSB,`MEMDB,`SYNC,`NOP,`MOVS,`STP:
|
fnNumReadPorts = 3'd0;
|
fnNumReadPorts = 3'd0;
|
`BR: fnNumReadPorts = 3'd0;
|
|
`LOOP: fnNumReadPorts = 3'd0;
|
|
`LDI,`LDIS,`IMM: fnNumReadPorts = 3'd0;
|
`LDI,`LDIS,`IMM: fnNumReadPorts = 3'd0;
|
`R,`P,`STI: fnNumReadPorts = 3'd1;
|
`R,`P,`STI: fnNumReadPorts = 3'd1;
|
`RTI,`RTD,`RTE: fnNumReadPorts = 3'd1;
|
`RTI,`RTD,`RTE: fnNumReadPorts = 3'd1;
|
`TST: fnNumReadPorts = 3'd1;
|
|
`ADDI,`ADDUI,`ADDUIS:
|
`ADDI,`ADDUI,`ADDUIS:
|
fnNumReadPorts = 3'd1;
|
fnNumReadPorts = 3'd1;
|
`_2ADDUI,`_4ADDUI,`_8ADDUI,`_16ADDUI:
|
`_2ADDUI,`_4ADDUI,`_8ADDUI,`_16ADDUI:
|
fnNumReadPorts = 3'd1;
|
fnNumReadPorts = 3'd1;
|
`SUBI,`SUBUI: fnNumReadPorts = 3'd1;
|
`SUBI,`SUBUI: fnNumReadPorts = 3'd1;
|
`CMPI: fnNumReadPorts = 3'd1;
|
|
`MULI,`MULUI,`DIVI,`DIVUI:
|
`MULI,`MULUI,`DIVI,`DIVUI:
|
fnNumReadPorts = 3'd1;
|
fnNumReadPorts = 3'd1;
|
`BITI,
|
`BITI,
|
`ANDI,`ORI,`EORI: fnNumReadPorts = 3'd1;
|
`ANDI,`ORI,`EORI: fnNumReadPorts = 3'd1;
|
`SHIFT:
|
`SHIFT:
|
| Line 1097... |
Line 1284... |
else
|
else
|
fnNumReadPorts = 3'd2;
|
fnNumReadPorts = 3'd2;
|
`RTS2,`CACHE,`LCL,`TLB,
|
`RTS2,`CACHE,`LCL,`TLB,
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,`LVWAR,`LWS,`LEA,`INC:
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,`LVWAR,`LWS,`LEA,`INC:
|
fnNumReadPorts = 3'd1;
|
fnNumReadPorts = 3'd1;
|
`JSR,`JSRS,`JSRZ,`SYS,`INT,`RTS,`BR,`LOOP:
|
`JSR,`JSRS,`JSRZ,`SYS,`INT,`RTS,`BR:
|
fnNumReadPorts = 3'd1;
|
fnNumReadPorts = 3'd1;
|
`SBX,`SCX,`SHX,`SWX,
|
`SBX,`SCX,`SHX,`SWX,
|
`MUX,`CAS,`STMV,`STCMP:
|
`MUX,`CAS,`STMV,`STCMP:
|
fnNumReadPorts = 3'd3;
|
fnNumReadPorts = 3'd3;
|
`MTSPR,`MFSPR,`POP,`UNLINK: fnNumReadPorts = 3'd1;
|
`MTSPR,`MFSPR,`POP,`UNLINK: fnNumReadPorts = 3'd1;
|
`STFND: fnNumReadPorts = 3'd2; // *** TLB reads on Rb we say 2 for simplicity
|
`STFND: fnNumReadPorts = 3'd2; // *** TLB reads on Rb we say 2 for simplicity
|
`BITFIELD:
|
`BITFIELD:
|
case(ins[43:40])
|
case(ins[43:40])
|
`BFSET,`BFCLR,`BFCHG,`BFEXT,`BFEXTU:
|
`BFSET,`BFCLR,`BFCHG,`BFEXT,`BFEXTU,`BFINSI:
|
fnNumReadPorts = 3'd1;
|
fnNumReadPorts = 3'd1;
|
`BFINS: fnNumReadPorts = 3'd2;
|
`BFINS: fnNumReadPorts = 3'd2;
|
default: fnNumReadPorts = 3'd0;
|
default: fnNumReadPorts = 3'd0;
|
endcase
|
endcase
|
|
default:
|
|
case(ins[15:12])
|
|
`TST: fnNumReadPorts = 3'd1;
|
|
`CMPI: fnNumReadPorts = 3'd1;
|
|
`CMP: fnNumReadPorts = 3'd2;
|
|
`BR: fnNumReadPorts = 3'd0;
|
default: fnNumReadPorts = 3'd2;
|
default: fnNumReadPorts = 3'd2;
|
endcase
|
endcase
|
|
endcase
|
endfunction
|
endfunction
|
|
|
function fnIsBranch;
|
function fnIsBranch;
|
input [7:0] opcode;
|
input [7:0] opcode;
|
casex(opcode)
|
case(opcode[7:4])
|
`BR: fnIsBranch = `TRUE;
|
`BR: fnIsBranch = `TRUE;
|
default: fnIsBranch = `FALSE;
|
default: fnIsBranch = `FALSE;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function fnIsPush;
|
function fnIsPush;
|
input [63:0] insn;
|
input [63:0] isn;
|
fnIsPush = insn[15:8]==`PUSH || insn[15:8]==`PEA;
|
fnIsPush = isn[15:8]==`PUSH || isn[15:8]==`PEA;
|
endfunction
|
endfunction
|
|
|
function fnIsPop;
|
function fnIsPop;
|
input [63:0] insn;
|
input [63:0] isn;
|
fnIsPop = insn[15:8]==`POP;
|
fnIsPop = isn[15:8]==`POP;
|
endfunction
|
endfunction
|
|
|
function fnIsStoreString;
|
function fnIsStoreString;
|
input [7:0] opcode;
|
input [7:0] opcode;
|
fnIsStoreString =
|
fnIsStoreString =
|
opcode==`STS;
|
opcode==`STS;
|
endfunction
|
endfunction
|
|
|
wire xbr = (iqentry_op[head0]==`BR) || (iqentry_op[head1]==`BR);
|
wire xbr = (iqentry_op[head0][7:4]==`BR) || (iqentry_op[head1][7:4]==`BR);
|
wire takb = (iqentry_op[head0]==`BR) ? commit0_v : commit1_v;
|
wire takb = (iqentry_op[head0][7:4]==`BR) ? commit0_v : commit1_v;
|
wire [DBW-1:0] xbrpc = (iqentry_op[head0]==`BR) ? iqentry_pc[head0] : iqentry_pc[head1];
|
wire [DBW-1:0] xbrpc = (iqentry_op[head0][7:4]==`BR) ? iqentry_pc[head0] : iqentry_pc[head1];
|
|
|
wire predict_takenA,predict_takenB,predict_takenC,predict_takenD;
|
wire predict_takenA,predict_takenB,predict_takenC,predict_takenD;
|
|
|
// There are really only two branch tables required one for fetchbuf0 and one
|
// There are really only two branch tables required one for fetchbuf0 and one
|
// for fetchbuf1. Synthesis removes the extra tables.
|
// for fetchbuf1. Synthesis removes the extra tables.
|
| Line 1196... |
Line 1390... |
.xpc(xbrpc),
|
.xpc(xbrpc),
|
.takb(takb),
|
.takb(takb),
|
.predict_taken(predict_takenD)
|
.predict_taken(predict_takenD)
|
);
|
);
|
|
|
`ifdef THREEWAY
|
|
Thor_BranchHistory #(DBW) ubhtE
|
|
(
|
|
.rst(rst_i),
|
|
.clk(clk),
|
|
.advanceX(xbr),
|
|
.xisBranch(xbr),
|
|
.pc(pc+fnInsnLength(insn)+fnInsnLength1(insn)),
|
|
.xpc(xbrpc),
|
|
.takb(takb),
|
|
.predict_taken(predict_takenE)
|
|
);
|
|
Thor_BranchHistory #(DBW) ubhtF
|
|
(
|
|
.rst(rst_i),
|
|
.clk(clk),
|
|
.advanceX(xbr),
|
|
.xisBranch(xbr),
|
|
.pc(pc+fnInsnLength(insn)+fnInsnLength1(insn)),
|
|
.xpc(xbrpc),
|
|
.takb(takb),
|
|
.predict_taken(predict_takenF)
|
|
);
|
|
`endif
|
|
|
|
Thor_icachemem #(DBW) uicm1
|
Thor_icachemem #(DBW) uicm1
|
(
|
(
|
.wclk(clk),
|
.wclk(clk),
|
.wce(cstate==ICACHE1),
|
.wce(cstate==ICACHE1),
|
.wr(ack_i|err_i),
|
.wr(ack_i|err_i),
|
| Line 1295... |
Line 1464... |
);
|
);
|
|
|
wire [DBW-1:0] shfto0,shfto1;
|
wire [DBW-1:0] shfto0,shfto1;
|
|
|
function fnIsShiftiop;
|
function fnIsShiftiop;
|
input [63:0] insn;
|
input [63:0] isn;
|
fnIsShiftiop = insn[15:8]==`SHIFT && (
|
fnIsShiftiop = isn[15:8]==`SHIFT && (
|
insn[39:34]==`SHLI || insn[39:34]==`SHLUI ||
|
isn[39:34]==`SHLI || isn[39:34]==`SHLUI ||
|
insn[39:34]==`SHRI || insn[39:34]==`SHRUI ||
|
isn[39:34]==`SHRI || isn[39:34]==`SHRUI ||
|
insn[39:34]==`ROLI || insn[39:34]==`RORI
|
isn[39:34]==`ROLI || isn[39:34]==`RORI
|
)
|
)
|
;
|
;
|
endfunction
|
endfunction
|
|
|
function fnIsShiftop;
|
function fnIsShiftop;
|
| Line 1321... |
Line 1490... |
// opcode==`FADD || opcode==`FSUB || opcode==`FMUL || opcode==`FDIV
|
// opcode==`FADD || opcode==`FSUB || opcode==`FMUL || opcode==`FDIV
|
// ;
|
// ;
|
endfunction
|
endfunction
|
|
|
function fnIsFPCtrl;
|
function fnIsFPCtrl;
|
input [63:0] insn;
|
input [63:0] isn;
|
fnIsFPCtrl = (insn[15:8]==`SINGLE_R && (insn[31:28]==`FTX||insn[31:28]==`FCX||insn[31:28]==`FDX||insn[31:28]==`FEX)) ||
|
fnIsFPCtrl = (isn[15:8]==`SINGLE_R && (isn[31:28]==`FTX||isn[31:28]==`FCX||isn[31:28]==`FDX||isn[31:28]==`FEX)) ||
|
(insn[15:8]==`DOUBLE_R && (insn[31:28]==`FRM))
|
(isn[15:8]==`DOUBLE_R && (isn[31:28]==`FRM))
|
;
|
;
|
endfunction
|
endfunction
|
|
|
function fnIsBitfield;
|
function fnIsBitfield;
|
input [7:0] opcode;
|
input [7:0] opcode;
|
fnIsBitfield = opcode==`BFSET || opcode==`BFCLR || opcode==`BFCHG || opcode==`BFINS || opcode==`BFEXT || opcode==`BFEXTU;
|
fnIsBitfield = opcode==`BITFIELD;
|
endfunction
|
endfunction
|
|
|
//wire [3:0] Pn = ir[7:4];
|
//wire [3:0] Pn = ir[7:4];
|
|
|
// Set the target register
|
// Set the target register
|
// 00-3F = general register file
|
// 00-3F = general register file
|
// 40-4F = predicate register
|
// 40-4F = predicate register
|
// 50-5F = code address register
|
// 50-5F = code address register
|
// 60-67 = segment base register
|
// 60-67 = segment base register
|
|
// 68-6F = segment limit register
|
// 70 = predicate register horizontal
|
// 70 = predicate register horizontal
|
// 73 = loop counter
|
// 73 = loop counter
|
function [6:0] fnTargetReg;
|
function [6:0] fnTargetReg;
|
input [63:0] ir;
|
input [63:0] ir;
|
begin
|
begin
|
if (ir[3:0]==4'h0) // Process special predicates
|
if (ir[3:0]==4'h0) // Process special predicates
|
fnTargetReg = 7'h000;
|
fnTargetReg = 7'h000;
|
else
|
else
|
casex(fnOpcode(ir))
|
case(fnOpcode(ir))
|
`POP: fnTargetReg = ir[22:16];
|
`POP: fnTargetReg = ir[22:16];
|
`LDI,`ADDUIS,`STS,`LINK,`UNLINK:
|
`LDI,`ADDUIS,`STS,`LINK,`UNLINK:
|
fnTargetReg = {1'b0,ir[21:16]};
|
fnTargetReg = {1'b0,ir[21:16]};
|
`LDIS:
|
`LDIS:
|
fnTargetReg = {1'b1,ir[21:16]};
|
fnTargetReg = {1'b1,ir[21:16]};
|
| Line 1381... |
Line 1551... |
fnTargetReg = 7'h00;
|
fnTargetReg = 7'h00;
|
`MFSPR:
|
`MFSPR:
|
fnTargetReg = {1'b0,ir[27:22]};
|
fnTargetReg = {1'b0,ir[27:22]};
|
`BITI:
|
`BITI:
|
fnTargetReg = {3'h4,ir[25:22]};
|
fnTargetReg = {3'h4,ir[25:22]};
|
`CMP,`CMPI,`TST:
|
// TST
|
|
8'h00,
|
|
8'h01,
|
|
8'h02,
|
|
8'h03,
|
|
8'h04,
|
|
8'h05,
|
|
8'h06,
|
|
8'h07,
|
|
8'h08,
|
|
8'h09,
|
|
8'h0A,
|
|
8'h0B,
|
|
8'h0C,
|
|
8'h0D,
|
|
8'h0E,
|
|
8'h0F,
|
|
// CMP
|
|
8'h10,
|
|
8'h11,
|
|
8'h12,
|
|
8'h13,
|
|
8'h14,
|
|
8'h15,
|
|
8'h16,
|
|
8'h17,
|
|
8'h18,
|
|
8'h19,
|
|
8'h1A,
|
|
8'h1B,
|
|
8'h1C,
|
|
8'h1D,
|
|
8'h1E,
|
|
8'h1F,
|
|
// CMPI
|
|
8'h20,
|
|
8'h21,
|
|
8'h22,
|
|
8'h23,
|
|
8'h24,
|
|
8'h25,
|
|
8'h26,
|
|
8'h27,
|
|
8'h28,
|
|
8'h29,
|
|
8'h2A,
|
|
8'h2B,
|
|
8'h2C,
|
|
8'h2D,
|
|
8'h2E,
|
|
8'h2F:
|
begin
|
begin
|
fnTargetReg = {3'h4,ir[11:8]};
|
fnTargetReg = {3'h4,ir[11:8]};
|
end
|
end
|
`SWCR: fnTargetReg = {3'h4,4'h0};
|
`SWCR: fnTargetReg = {3'h4,4'h0};
|
`JSR,`JSRZ,`JSRS,`SYS,`INT:
|
`JSR,`JSRZ,`JSRS,`SYS,`INT:
|
| Line 1473... |
Line 1693... |
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function fnHasConst;
|
function fnHasConst;
|
input [7:0] opcode;
|
input [7:0] opcode;
|
casex(opcode)
|
case(opcode)
|
`BFCLR,`BFSET,`BFCHG,`BFEXT,`BFEXTU,`BFINS,
|
`BFCLR,`BFSET,`BFCHG,`BFEXT,`BFEXTU,`BFINS,
|
`LDI,`LDIS,`ADDUIS,
|
`LDI,`LDIS,`ADDUIS,
|
`ADDI,`SUBI,`ADDUI,`SUBUI,`MULI,`MULUI,`DIVI,`DIVUI,
|
`ADDI,`SUBI,`ADDUI,`SUBUI,`MULI,`MULUI,`DIVI,`DIVUI,
|
`_2ADDUI,`_4ADDUI,`_8ADDUI,`_16ADDUI,
|
`_2ADDUI,`_4ADDUI,`_8ADDUI,`_16ADDUI,
|
`CMPI,
|
// CMPI
|
|
8'h20,
|
|
8'h21,
|
|
8'h22,
|
|
8'h23,
|
|
8'h24,
|
|
8'h25,
|
|
8'h26,
|
|
8'h27,
|
|
8'h28,
|
|
8'h29,
|
|
8'h2A,
|
|
8'h2B,
|
|
8'h2C,
|
|
8'h2D,
|
|
8'h2E,
|
|
8'h2F,
|
|
// BR
|
|
8'h30,
|
|
8'h31,
|
|
8'h32,
|
|
8'h33,
|
|
8'h34,
|
|
8'h35,
|
|
8'h36,
|
|
8'h37,
|
|
8'h38,
|
|
8'h39,
|
|
8'h3A,
|
|
8'h3B,
|
|
8'h3C,
|
|
8'h3D,
|
|
8'h3E,
|
|
8'h3F,
|
`ANDI,`ORI,`EORI,`BITI,
|
`ANDI,`ORI,`EORI,`BITI,
|
// `SHLI,`SHLUI,`SHRI,`SHRUI,`ROLI,`RORI,
|
// `SHLI,`SHLUI,`SHRI,`SHRUI,`ROLI,`RORI,
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWS,`LEA,`INC,
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LWS,`LEA,`INC,
|
`LVB,`LVC,`LVH,`LVW,`LVWAR,`STI,
|
`LVB,`LVC,`LVH,`LVW,`LVWAR,`STI,
|
`SB,`SC,`SH,`SW,`SWCR,`CAS,`SWS,
|
`SB,`SC,`SH,`SW,`SWCR,`CAS,`SWS,
|
`JSR,`JSRS,`SYS,`INT,`BR,`RTS2,`LOOP,`PEA,`LINK,`UNLINK:
|
`JSR,`JSRS,`SYS,`INT,`RTS2,`LOOP,`PEA,`LINK,`UNLINK:
|
fnHasConst = 1'b1;
|
fnHasConst = 1'b1;
|
default:
|
default:
|
fnHasConst = 1'b0;
|
fnHasConst = 1'b0;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function fnIsFlowCtrl;
|
function fnIsFlowCtrl;
|
input [7:0] opcode;
|
input [7:0] opcode;
|
begin
|
begin
|
casex(opcode)
|
case(opcode)
|
`JSR,`JSRS,`JSRZ,`SYS,`INT,`LOOP,`BR,`RTS,`RTS2,`RTI,`RTD,`RTE:
|
`JSR,`JSRS,`JSRZ,`SYS,`INT,`LOOP,`RTS,`RTS2,`RTI,`RTD,`RTE:
|
|
fnIsFlowCtrl = 1'b1;
|
|
default:
|
|
if (opcode[7:4]==`BR)
|
fnIsFlowCtrl = 1'b1;
|
fnIsFlowCtrl = 1'b1;
|
default: fnIsFlowCtrl = 1'b0;
|
else
|
|
fnIsFlowCtrl = 1'b0;
|
endcase
|
endcase
|
end
|
end
|
endfunction
|
endfunction
|
|
|
// fnCanException
|
// fnCanException
|
| Line 1515... |
Line 1772... |
`FLOAT:
|
`FLOAT:
|
case(func)
|
case(func)
|
`FDIVS,`FMULS,`FADDS,`FSUBS,
|
`FDIVS,`FMULS,`FADDS,`FSUBS,
|
`FDIV,`FMUL,`FADD,`FSUB:
|
`FDIV,`FMUL,`FADD,`FSUB:
|
fnCanException = `TRUE;
|
fnCanException = `TRUE;
|
|
default: fnCanException = `FALSE;
|
endcase
|
endcase
|
`SINGLE_R:
|
`SINGLE_R:
|
if (func==`FTX) fnCanException = `TRUE;
|
if (func==`FTX) fnCanException = `TRUE;
|
|
else fnCanException = `FALSE;
|
`ADD,`ADDI,`SUB,`SUBI,`DIV,`DIVI,`MUL,`MULI:
|
`ADD,`ADDI,`SUB,`SUBI,`DIV,`DIVI,`MUL,`MULI:
|
fnCanException = `TRUE;
|
fnCanException = `TRUE;
|
`TLB,`RTI,`RTD,`RTE,`CLI,`SEI:
|
`TLB,`RTI,`RTD,`RTE,`CLI,`SEI:
|
fnCanException = `TRUE;
|
fnCanException = `TRUE;
|
default:
|
default:
|
| Line 1532... |
Line 1791... |
// fnInsnLength
|
// fnInsnLength
|
// Used by fetch logic.
|
// Used by fetch logic.
|
// Return the length of an instruction.
|
// Return the length of an instruction.
|
//
|
//
|
function [3:0] fnInsnLength;
|
function [3:0] fnInsnLength;
|
input [127:0] insn;
|
input [127:0] isn;
|
casex(insn[15:0])
|
case(isn[7:0])
|
16'bxxxxxxxx00000000: fnInsnLength = 4'd1; // BRK
|
8'b00000000: fnInsnLength = 4'd1; // BRK
|
16'bxxxxxxxx00010000: fnInsnLength = 4'd1; // NOP
|
8'b00010000: fnInsnLength = 4'd1; // NOP
|
16'bxxxxxxxx00100000: fnInsnLength = 4'd2;
|
8'b00100000: fnInsnLength = 4'd2;
|
16'bxxxxxxxx00110000: fnInsnLength = 4'd3;
|
8'b00110000: fnInsnLength = 4'd3;
|
16'bxxxxxxxx01000000: fnInsnLength = 4'd4;
|
8'b01000000: fnInsnLength = 4'd4;
|
16'bxxxxxxxx01010000: fnInsnLength = 4'd5;
|
8'b01010000: fnInsnLength = 4'd5;
|
16'bxxxxxxxx01100000: fnInsnLength = 4'd6;
|
8'b01100000: fnInsnLength = 4'd6;
|
16'bxxxxxxxx01110000: fnInsnLength = 4'd7;
|
8'b01110000: fnInsnLength = 4'd7;
|
16'bxxxxxxxx10000000: fnInsnLength = 4'd8;
|
8'b10000000: fnInsnLength = 4'd8;
|
16'bxxxxxxxx00010001: fnInsnLength = 4'd1; // RTS short form
|
8'b00010001: fnInsnLength = 4'd1; // RTS short form
|
default:
|
default:
|
casex(insn[15:8])
|
case(isn[15:8])
|
`NOP,`SEI,`CLI,`RTI,`RTD,`RTE,`MEMSB,`MEMDB,`SYNC:
|
`NOP,`SEI,`CLI,`RTI,`RTD,`RTE,`MEMSB,`MEMDB,`SYNC:
|
fnInsnLength = 4'd2;
|
fnInsnLength = 4'd2;
|
`TST,`BR,`JSRZ,`RTS,`CACHE,`LOOP,`PUSH,`POP,`UNLINK:
|
`JSRZ,`RTS,`CACHE,`LOOP,`PUSH,`POP,`UNLINK:
|
fnInsnLength = 4'd3;
|
fnInsnLength = 4'd3;
|
`SYS,`CMP,`CMPI,`MTSPR,`MFSPR,`LDI,`LDIS,`ADDUIS,`R,`TLB,`MOVS,`RTS2,`STP:
|
`SYS,`MTSPR,`MFSPR,`LDI,`LDIS,`ADDUIS,`R,`TLB,`MOVS,`RTS2,`STP:
|
fnInsnLength = 4'd4;
|
fnInsnLength = 4'd4;
|
`BITFIELD,`JSR,`MUX,`BCD,`INC:
|
`BITFIELD,`JSR,`MUX,`BCD,`INC:
|
fnInsnLength = 4'd6;
|
fnInsnLength = 4'd6;
|
`CAS:
|
`CAS:
|
fnInsnLength = 4'd6;
|
fnInsnLength = 4'd6;
|
default:
|
default:
|
fnInsnLength = 4'd5;
|
begin
|
|
case(isn[15:12])
|
|
`TST: fnInsnLength = 4'd3;
|
|
`BR: fnInsnLength = 4'd3;
|
|
`CMP,`CMPI: fnInsnLength = 4'd4;
|
|
default: fnInsnLength = 4'd5;
|
|
endcase
|
|
end
|
endcase
|
endcase
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [3:0] fnInsnLength1;
|
function [3:0] fnInsnLength1;
|
input [127:0] insn;
|
input [127:0] isn;
|
case(fnInsnLength(insn))
|
case(fnInsnLength(isn))
|
4'd1: fnInsnLength1 = fnInsnLength(insn[127: 8]);
|
4'd1: fnInsnLength1 = fnInsnLength(isn[127: 8]);
|
4'd2: fnInsnLength1 = fnInsnLength(insn[127:16]);
|
4'd2: fnInsnLength1 = fnInsnLength(isn[127:16]);
|
4'd3: fnInsnLength1 = fnInsnLength(insn[127:24]);
|
4'd3: fnInsnLength1 = fnInsnLength(isn[127:24]);
|
4'd4: fnInsnLength1 = fnInsnLength(insn[127:32]);
|
4'd4: fnInsnLength1 = fnInsnLength(isn[127:32]);
|
4'd5: fnInsnLength1 = fnInsnLength(insn[127:40]);
|
4'd5: fnInsnLength1 = fnInsnLength(isn[127:40]);
|
4'd6: fnInsnLength1 = fnInsnLength(insn[127:48]);
|
4'd6: fnInsnLength1 = fnInsnLength(isn[127:48]);
|
4'd7: fnInsnLength1 = fnInsnLength(insn[127:56]);
|
4'd7: fnInsnLength1 = fnInsnLength(isn[127:56]);
|
4'd8: fnInsnLength1 = fnInsnLength(insn[127:64]);
|
4'd8: fnInsnLength1 = fnInsnLength(isn[127:64]);
|
default: fnInsnLength1 = 4'd0;
|
default: fnInsnLength1 = 4'd0;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
function [3:0] fnInsnLength2;
|
function [3:0] fnInsnLength2;
|
input [127:0] insn;
|
input [127:0] isn;
|
case(fnInsnLength(insn)+fnInsnLength1(insn))
|
case(fnInsnLength(isn)+fnInsnLength1(isn))
|
4'd2: fnInsnLength2 = fnInsnLength(insn[127:16]);
|
4'd2: fnInsnLength2 = fnInsnLength(isn[127:16]);
|
4'd3: fnInsnLength2 = fnInsnLength(insn[127:24]);
|
4'd3: fnInsnLength2 = fnInsnLength(isn[127:24]);
|
4'd4: fnInsnLength2 = fnInsnLength(insn[127:32]);
|
4'd4: fnInsnLength2 = fnInsnLength(isn[127:32]);
|
4'd5: fnInsnLength2 = fnInsnLength(insn[127:40]);
|
4'd5: fnInsnLength2 = fnInsnLength(isn[127:40]);
|
4'd6: fnInsnLength2 = fnInsnLength(insn[127:48]);
|
4'd6: fnInsnLength2 = fnInsnLength(isn[127:48]);
|
4'd7: fnInsnLength2 = fnInsnLength(insn[127:56]);
|
4'd7: fnInsnLength2 = fnInsnLength(isn[127:56]);
|
4'd8: fnInsnLength2 = fnInsnLength(insn[127:64]);
|
4'd8: fnInsnLength2 = fnInsnLength(isn[127:64]);
|
4'd9: fnInsnLength2 = fnInsnLength(insn[127:72]);
|
4'd9: fnInsnLength2 = fnInsnLength(isn[127:72]);
|
4'd10: fnInsnLength2 = fnInsnLength(insn[127:80]);
|
4'd10: fnInsnLength2 = fnInsnLength(isn[127:80]);
|
4'd11: fnInsnLength2 = fnInsnLength(insn[127:88]);
|
4'd11: fnInsnLength2 = fnInsnLength(isn[127:88]);
|
4'd12: fnInsnLength2 = fnInsnLength(insn[127:96]);
|
4'd12: fnInsnLength2 = fnInsnLength(isn[127:96]);
|
4'd13: fnInsnLength2 = fnInsnLength(insn[127:104]);
|
4'd13: fnInsnLength2 = fnInsnLength(isn[127:104]);
|
4'd14: fnInsnLength2 = fnInsnLength(insn[127:112]);
|
4'd14: fnInsnLength2 = fnInsnLength(isn[127:112]);
|
4'd15: fnInsnLength2 = fnInsnLength(insn[127:120]);
|
4'd15: fnInsnLength2 = fnInsnLength(isn[127:120]);
|
default: fnInsnLength2 = 4'd0;
|
default: fnInsnLength2 = 4'd0;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
wire [5:0] total_insn_length = fnInsnLength(insn) + fnInsnLength1(insn) + fnInsnLength2(insn);
|
wire [5:0] total_insn_length = fnInsnLength(insn) + fnInsnLength1(insn) + fnInsnLength2(insn);
|
| Line 1606... |
Line 1872... |
|
|
always @(fetchbuf or fetchbufA_instr or fetchbufA_v or fetchbufA_pc
|
always @(fetchbuf or fetchbufA_instr or fetchbufA_v or fetchbufA_pc
|
or fetchbufB_instr or fetchbufB_v or fetchbufB_pc
|
or fetchbufB_instr or fetchbufB_v or fetchbufB_pc
|
or fetchbufC_instr or fetchbufC_v or fetchbufC_pc
|
or fetchbufC_instr or fetchbufC_v or fetchbufC_pc
|
or fetchbufD_instr or fetchbufD_v or fetchbufD_pc
|
or fetchbufD_instr or fetchbufD_v or fetchbufD_pc
|
`ifdef THREEWAY
|
|
or fetchbufE_instr or fetchbufE_v or fetchbufE_pc
|
|
or fetchbufF_instr or fetchbufF_v or fetchbufF_pc
|
|
`endif
|
|
)
|
)
|
begin
|
begin
|
fetchbuf0_instr <= (fetchbuf == 1'b0) ? fetchbufA_instr : fetchbufC_instr;
|
fetchbuf0_instr <= (fetchbuf == 1'b0) ? fetchbufA_instr : fetchbufC_instr;
|
fetchbuf0_v <= (fetchbuf == 1'b0) ? fetchbufA_v : fetchbufC_v ;
|
fetchbuf0_v <= (fetchbuf == 1'b0) ? fetchbufA_v : fetchbufC_v ;
|
|
|
| Line 1673... |
Line 1935... |
opcode==`ADDI || opcode==`SUBI || opcode==`ADDUI || opcode==`SUBUI || opcode==`MULI || opcode==`MULUI || opcode==`DIVI || opcode==`DIVUI ||
|
opcode==`ADDI || opcode==`SUBI || opcode==`ADDUI || opcode==`SUBUI || opcode==`MULI || opcode==`MULUI || opcode==`DIVI || opcode==`DIVUI ||
|
opcode==`ANDI || opcode==`ORI || opcode==`EORI ||
|
opcode==`ANDI || opcode==`ORI || opcode==`EORI ||
|
opcode==`ADD || opcode==`SUB || opcode==`ADDU || opcode==`SUBU || opcode==`MUL || opcode==`MULU || opcode==`DIV || opcode==`DIVU ||
|
opcode==`ADD || opcode==`SUB || opcode==`ADDU || opcode==`SUBU || opcode==`MUL || opcode==`MULU || opcode==`DIV || opcode==`DIVU ||
|
opcode==`AND || opcode==`OR || opcode==`EOR || opcode==`NAND || opcode==`NOR || opcode==`ENOR || opcode==`ANDC || opcode==`ORC ||
|
opcode==`AND || opcode==`OR || opcode==`EOR || opcode==`NAND || opcode==`NOR || opcode==`ENOR || opcode==`ANDC || opcode==`ORC ||
|
opcode==`SHIFT ||
|
opcode==`SHIFT ||
|
opcode==`R || opcode==`RR || opcode==`LEA || opcode==`P ||
|
opcode==`R || opcode==`RR || opcode==`LEA || opcode==`P || opcode==`LOOP ||
|
|
opcode==`BITI || opcode==`CMP || opcode==`CMPI || opcode==`TST ||
|
opcode==`LDI || opcode==`LDIS || opcode==`ADDUIS || opcode==`MFSPR ||
|
opcode==`LDI || opcode==`LDIS || opcode==`ADDUIS || opcode==`MFSPR ||
|
// Branch registers / Segment registers
|
// Branch registers / Segment registers
|
((opcode==`MTSPR || opcode==`MOVS) /*&& (fnTargetsCa(ir) || fnTargetsSegreg(ir))*/) ||
|
((opcode==`MTSPR || opcode==`MOVS) /*&& (fnTargetsCa(ir) || fnTargetsSegreg(ir))*/) ||
|
opcode==`JSR || opcode==`JSRS || opcode==`JSRZ || opcode==`SYS || opcode==`INT ||
|
opcode==`JSR || opcode==`JSRS || opcode==`JSRZ || opcode==`SYS || opcode==`INT ||
|
// predicate registers
|
// predicate registers
|
| Line 1715... |
Line 1978... |
input [7:0] opcode;
|
input [7:0] opcode;
|
fnIsIndexed = opcode==`LBX || opcode==`LBUX || opcode==`LCX || opcode==`LCUX || opcode==`LHX || opcode==`LHUX || opcode==`LWX ||
|
fnIsIndexed = opcode==`LBX || opcode==`LBUX || opcode==`LCX || opcode==`LCUX || opcode==`LHX || opcode==`LHUX || opcode==`LWX ||
|
opcode==`SBX || opcode==`SCX || opcode==`SHX || opcode==`SWX;
|
opcode==`SBX || opcode==`SCX || opcode==`SHX || opcode==`SWX;
|
endfunction
|
endfunction
|
|
|
// *** check these
|
//
|
function fnIsPFW;
|
function fnIsPFW;
|
input [7:0] opcode;
|
input [7:0] opcode;
|
fnIsPFW = opcode[7:4]<4'h3 || opcode==`BITI || opcode==`P;//opcode==`CMP || opcode==`CMPI || opcode==`TST;
|
fnIsPFW = opcode[7:4]<4'h3 || opcode==`BITI || opcode==`P;//opcode==`CMP || opcode==`CMPI || opcode==`TST;
|
endfunction
|
endfunction
|
|
|
|
// Decoding for illegal opcodes
|
|
function fnIsIllegal;
|
|
input [7:0] op;
|
|
input [5:0] fn;
|
|
casex(op)
|
|
8'h40:
|
|
if (fn > 6'h11)
|
|
fnIsIllegal = `TRUE;
|
|
else if (fn==6'hC || fn==6'hD || fn==6'hE || fn==6'hF)
|
|
fnIsIllegal = `TRUE;
|
|
else fnIsIllegal = `FALSE;
|
|
8'h41:
|
|
if (fn > 6'd3) fnIsIllegal = `TRUE;
|
|
else fnIsIllegal = `FALSE;
|
|
8'h42:
|
|
if (fn > 6'd7) fnIsIllegal = `TRUE;
|
|
else fnIsIllegal = `FALSE;
|
|
8'h50:
|
|
if (fn > 6'd7) fnIsIllegal = `TRUE;
|
|
else fnIsIllegal = `FALSE;
|
|
8'h58:
|
|
if (fn > 6'h15 || (fn > 6'h5 && fn < 6'h10))
|
|
fnIsIllegal = `TRUE;
|
|
else
|
|
fnIsIllegal = `FALSE;
|
|
8'h77:
|
|
if (fn==8'h99 || fn==8'h9A || fn==8'h9B || fn==8'h9E || fn==8'h9F)
|
|
fnIsIllegal = `TRUE;
|
|
else
|
|
fnIsIllegal = `FALSE;
|
|
8'h78:
|
|
if ((fn >= 8'h07 && fn <= 8'h0B) || (fn >= 8'h17 && fn <= 8'h1B))
|
|
fnIsIllegal = `FALSE;
|
|
else
|
|
fnIsIllegal = `TRUE;
|
|
8'h79:
|
|
if (fn==8'h99 || fn==8'h9A || fn==8'h9B)
|
|
fnIsIllegal = `TRUE;
|
|
else
|
|
fnIsIllegal = `FALSE;
|
|
8'hAA:
|
|
if (fn > 4'd6)
|
|
fnIsIllegal = `TRUE;
|
|
else
|
|
fnIsIllegal = `FALSE;
|
|
8'hF5:
|
|
if (fn > 4'd2)
|
|
fnIsIllegal = `TRUE;
|
|
else
|
|
fnIsIllegal = `FALSE;
|
|
8'h43,8'h44,8'h45: fnIsIllegal = `TRUE;
|
|
8'h52,8'h56,8'h57,8'h59,8'h5A,8'h5B,8'h5C,8'h5D,8'h5E,8'h5F:
|
|
fnIsIllegal = `TRUE;
|
|
8'h60,8'h61,8'h62,8'h63,8'h64,8'h65,8'h66,8'h67,8'h68,8'h69,8'h6A:
|
|
fnIsIllegal = `TRUE;
|
|
8'h73,8'h74,8'h75,8'h76,8'h7A,8'h7B,8'h7C,8'h7D,8'h7E,8'h7F:
|
|
fnIsIllegal = `TRUE;
|
|
8'h87,8'h88,8'h89,8'h8A,8'h8D:
|
|
fnIsIllegal = `TRUE;
|
|
8'h94,8'h95,8'h9C:
|
|
fnIsIllegal = `TRUE;
|
|
8'hB7,8'b10111xxx:
|
|
fnIsIllegal = `TRUE;
|
|
8'hC4,8'hC5,8'b11001xxx:
|
|
fnIsIllegal = `TRUE;
|
|
8'hDx: fnIsIllegal = `TRUE;
|
|
8'hEx: fnIsIllegal = `TRUE;
|
|
8'hFD,8'hFE: fnIsIllegal = `TRUE;
|
|
default: fnIsIllegal = `FALSE;
|
|
endcase
|
|
endfunction
|
|
|
function [7:0] fnSelect;
|
function [7:0] fnSelect;
|
input [7:0] opcode;
|
input [7:0] opcode;
|
input [5:0] fn;
|
input [5:0] fn;
|
input [DBW-1:0] adr;
|
input [DBW-1:0] adr;
|
begin
|
begin
|
| Line 1882... |
Line 2217... |
case(sel[3:0])
|
case(sel[3:0])
|
4'h3: fnDatai = dat[15:0];
|
4'h3: fnDatai = dat[15:0];
|
4'hC: fnDatai = dat[31:16];
|
4'hC: fnDatai = dat[31:16];
|
default: fnDatai = {DBW{1'b1}};
|
default: fnDatai = {DBW{1'b1}};
|
endcase
|
endcase
|
`LH,`LHU,`LW,`LWX,`LVH,`LVW,`LVWAR,`LHX,`LHUX,`CAS,`LWS,`LCL,`POP,`UNLINK:
|
`LH,`LHU,`LW,`LWX,`LVH,`LVW,`LVWAR,`LHX,`LHUX,`CAS,`LCL,`LWS,`POP,`UNLINK:
|
fnDatai = dat[31:0];
|
fnDatai = dat[31:0];
|
default: fnDatai = {DBW{1'b1}};
|
default: fnDatai = {DBW{1'b1}};
|
endcase
|
endcase
|
else
|
else
|
case(opcode)
|
case(opcode)
|
| Line 1970... |
Line 2305... |
case(sel)
|
case(sel)
|
8'h0F: fnDatai = dat[DBW/2-1:0];
|
8'h0F: fnDatai = dat[DBW/2-1:0];
|
8'hF0: fnDatai = dat[DBW-1:DBW/2];
|
8'hF0: fnDatai = dat[DBW-1:DBW/2];
|
default: fnDatai = {DBW{1'b1}};
|
default: fnDatai = {DBW{1'b1}};
|
endcase
|
endcase
|
`LW,`LWX,`LVW,`LVWAR,`CAS,`LWS,`LCL,`POP,`UNLINK:
|
`LW,`LWX,`LVW,`LVWAR,`CAS,`LCL,`LWS,`POP,`UNLINK:
|
case(sel)
|
case(sel)
|
8'hFF: fnDatai = dat;
|
8'hFF: fnDatai = dat;
|
default: fnDatai = {DBW{1'b1}};
|
default: fnDatai = {DBW{1'b1}};
|
endcase
|
endcase
|
default: fnDatai = {DBW{1'b1}};
|
default: fnDatai = {DBW{1'b1}};
|
| Line 2077... |
Line 2412... |
branch_pc <= {{ABW-8{1'b1}},8'h80}; // set to something to prevent a latch
|
branch_pc <= {{ABW-8{1'b1}},8'h80}; // set to something to prevent a latch
|
end
|
end
|
|
|
assign int_pending = (nmi_edge & ~StatusHWI & ~int_commit) || (irq_i & ~im & ~StatusHWI & ~int_commit);
|
assign int_pending = (nmi_edge & ~StatusHWI & ~int_commit) || (irq_i & ~im & ~StatusHWI & ~int_commit);
|
|
|
assign mem_stringmiss = ((dram0_op==`STS || dram0_op==`STFND) && int_pending && lc != 0) ||
|
assign mem_stringmissx = ((dram0_op==`STS || dram0_op==`STFND) && int_pending && lc != 0) ||
|
((dram0_op==`STMV || dram0_op==`STCMP) && int_pending && lc != 0 && stmv_flag);
|
((dram0_op==`STMV || dram0_op==`STCMP) && int_pending && lc != 0 && stmv_flag);
|
|
|
// "Stream" interrupt instructions into the instruction stream until an INT
|
// "Stream" interrupt instructions into the instruction stream until an INT
|
// instruction commits. This avoids the problem of an INT instruction being
|
// instruction commits. This avoids the problem of an INT instruction being
|
// stomped on by a previous branch instruction.
|
// stomped on by a previous branch instruction.
|
| Line 2157... |
Line 2492... |
endcase
|
endcase
|
|
|
// Return the immediate field of an instruction
|
// Return the immediate field of an instruction
|
function [63:0] fnImm;
|
function [63:0] fnImm;
|
input [127:0] insn;
|
input [127:0] insn;
|
casex(insn[15:0])
|
case(insn[7:0])
|
16'bxxxxxxxx00010001: // RTS short form
|
8'b00010001: // RTS short form
|
fnImm = 64'd0;
|
fnImm = 64'd0;
|
default:
|
default:
|
casex(insn[15:8])
|
case(insn[15:8])
|
`P: fnImm = insn[33:16];
|
`P: fnImm = insn[33:16];
|
`CAS: fnImm = {{56{insn[47]}},insn[47:40]};
|
`CAS: fnImm = {{56{insn[47]}},insn[47:40]};
|
`BCD: fnImm = insn[47:40];
|
`BCD: fnImm = insn[47:40];
|
`TLB: fnImm = insn[23:16];
|
`TLB: fnImm = insn[23:16];
|
`LOOP: fnImm = {{56{insn[23]}},insn[23:16]};
|
`LOOP: fnImm = {{56{insn[23]}},insn[23:16]};
|
| Line 2173... |
Line 2508... |
`JSR: fnImm = {{40{insn[47]}},insn[47:24]};
|
`JSR: fnImm = {{40{insn[47]}},insn[47:24]};
|
`JSRS: fnImm = {{48{insn[39]}},insn[39:24]};
|
`JSRS: fnImm = {{48{insn[39]}},insn[39:24]};
|
`BITFIELD: fnImm = insn[47:32];
|
`BITFIELD: fnImm = insn[47:32];
|
`SYS,`INT: fnImm = insn[31:24];
|
`SYS,`INT: fnImm = insn[31:24];
|
`RTS2: fnImm = {insn[31:27],3'b000};
|
`RTS2: fnImm = {insn[31:27],3'b000};
|
`CMPI,`LDI,`LDIS,`ADDUIS:
|
//`CMPI,
|
|
8'h20,
|
|
8'h21,
|
|
8'h22,
|
|
8'h23,
|
|
8'h24,
|
|
8'h25,
|
|
8'h26,
|
|
8'h27,
|
|
8'h28,
|
|
8'h29,
|
|
8'h2A,
|
|
8'h2B,
|
|
8'h2C,
|
|
8'h2D,
|
|
8'h2E,
|
|
8'h2F,
|
|
`LDI,`LDIS,`ADDUIS:
|
fnImm = {{54{insn[31]}},insn[31:22]};
|
fnImm = {{54{insn[31]}},insn[31:22]};
|
`RTS: fnImm = insn[19:16];
|
`RTS: fnImm = insn[19:16];
|
`RTD,`RTE,`RTI,`JSRZ,`STMV,`STCMP,`STFND,`CACHE,`STS: fnImm = 8'h00;
|
`RTD,`RTE,`RTI,`JSRZ,`STMV,`STCMP,`STFND,`CACHE,`STS: fnImm = 8'h00;
|
`STI: fnImm = {{58{insn[33]}},insn[33:28]};
|
`STI: fnImm = {{58{insn[33]}},insn[33:28]};
|
//`LINK: fnImm = {insn[39:28],3'b000};
|
//`LINK: fnImm = {insn[39:28],3'b000};
|
| Line 2194... |
Line 2546... |
function [7:0] fnImm8;
|
function [7:0] fnImm8;
|
input [127:0] insn;
|
input [127:0] insn;
|
if (insn[7:0]==8'h11)
|
if (insn[7:0]==8'h11)
|
fnImm8 = 8'h00;
|
fnImm8 = 8'h00;
|
else
|
else
|
casex(insn[15:8])
|
case(insn[15:8])
|
`CAS: fnImm8 = insn[47:40];
|
`CAS: fnImm8 = insn[47:40];
|
`BCD: fnImm8 = insn[47:40];
|
`BCD: fnImm8 = insn[47:40];
|
`TLB: fnImm8 = insn[23:16];
|
`TLB: fnImm8 = insn[23:16];
|
`LOOP: fnImm8 = insn[23:16];
|
`LOOP: fnImm8 = insn[23:16];
|
`STP: fnImm8 = insn[23:16];
|
`STP: fnImm8 = insn[23:16];
|
`JSR,`JSRS,`RTS2: fnImm8 = insn[31:24];
|
`JSR,`JSRS,`RTS2: fnImm8 = insn[31:24];
|
`BITFIELD: fnImm8 = insn[39:32];
|
`BITFIELD: fnImm8 = insn[39:32];
|
`SYS,`INT: fnImm8 = insn[31:24];
|
`SYS,`INT: fnImm8 = insn[31:24];
|
`CMPI,`LDI,`LDIS,`ADDUIS: fnImm8 = insn[29:22];
|
//`CMPI,
|
|
8'h20,
|
|
8'h21,
|
|
8'h22,
|
|
8'h23,
|
|
8'h24,
|
|
8'h25,
|
|
8'h26,
|
|
8'h27,
|
|
8'h28,
|
|
8'h29,
|
|
8'h2A,
|
|
8'h2B,
|
|
8'h2C,
|
|
8'h2D,
|
|
8'h2E,
|
|
8'h2F,
|
|
`LDI,`LDIS,`ADDUIS: fnImm8 = insn[29:22];
|
`RTS: fnImm8 = insn[19:16];
|
`RTS: fnImm8 = insn[19:16];
|
`RTD,`RTE,`RTI,`JSRZ,`STMV,`STCMP,`STFND,`CACHE,`STS: fnImm8 = 8'h00;
|
`RTD,`RTE,`RTI,`JSRZ,`STMV,`STCMP,`STFND,`CACHE,`STS: fnImm8 = 8'h00;
|
`STI: fnImm8 = insn[35:28];
|
`STI: fnImm8 = insn[35:28];
|
//`LINK: fnImm8 = {insn[32:28],3'b000};
|
`ifdef STACKOPS
|
|
`LINK: fnImm8 = {insn[32:28],3'b000};
|
|
`endif
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,`LVWAR,
|
`LB,`LBU,`LC,`LCU,`LH,`LHU,`LW,`LVB,`LVC,`LVH,`LVW,`LVWAR,
|
`SB,`SC,`SH,`SW,`SWCR,`LWS,`SWS,`INC,`LCL,`PEA:
|
`SB,`SC,`SH,`SW,`SWCR,`LWS,`SWS,`INC,`LCL,`PEA:
|
fnImm8 = insn[35:28];
|
fnImm8 = insn[35:28];
|
default: fnImm8 = insn[35:28];
|
default: fnImm8 = insn[35:28];
|
endcase
|
endcase
|
| Line 2221... |
Line 2592... |
function fnImmMSB;
|
function fnImmMSB;
|
input [127:0] insn;
|
input [127:0] insn;
|
if (insn[7:0]==8'h11)
|
if (insn[7:0]==8'h11)
|
fnImmMSB = 1'b0;
|
fnImmMSB = 1'b0;
|
else
|
else
|
casex(insn[15:8])
|
case(insn[15:8])
|
`CAS: fnImmMSB = insn[47];
|
`CAS: fnImmMSB = insn[47];
|
`TLB,`BCD,`STP:
|
`TLB,`BCD,`STP:
|
fnImmMSB = 1'b0; // TLB regno is unsigned
|
fnImmMSB = 1'b0; // TLB regno is unsigned
|
`LOOP:
|
`LOOP:
|
fnImmMSB = insn[23];
|
fnImmMSB = insn[23];
|
`JSR:
|
`JSR:
|
fnImmMSB = insn[47];
|
fnImmMSB = insn[47];
|
`JSRS:
|
`JSRS:
|
fnImmMSB = insn[39];
|
fnImmMSB = insn[39];
|
`CMPI,`LDI,`LDIS,`ADDUIS:
|
//`CMPI,
|
|
8'h20,
|
|
8'h21,
|
|
8'h22,
|
|
8'h23,
|
|
8'h24,
|
|
8'h25,
|
|
8'h26,
|
|
8'h27,
|
|
8'h28,
|
|
8'h29,
|
|
8'h2A,
|
|
8'h2B,
|
|
8'h2C,
|
|
8'h2D,
|
|
8'h2E,
|
|
8'h2F,
|
|
`LDI,`LDIS,`ADDUIS:
|
fnImmMSB = insn[31];
|
fnImmMSB = insn[31];
|
`SYS,`INT,`CACHE,`LINK:
|
`SYS,`INT,`CACHE,`LINK:
|
fnImmMSB = 1'b0; // SYS,INT are unsigned
|
fnImmMSB = 1'b0; // SYS,INT are unsigned
|
`RTS,`RTD,`RTE,`RTI,`JSRZ,`STMV,`STCMP,`STFND,`RTS2,`STS:
|
`RTS,`RTD,`RTE,`RTI,`JSRZ,`STMV,`STCMP,`STFND,`RTS2,`STS:
|
fnImmMSB = 1'b0; // RTS is unsigned
|
fnImmMSB = 1'b0; // RTS is unsigned
|
| Line 2263... |
Line 2651... |
4'd8: fnImmImm = {insn[63:8],8'h00};
|
4'd8: fnImmImm = {insn[63:8],8'h00};
|
default: fnImmImm = 64'd0;
|
default: fnImmImm = 64'd0;
|
endcase
|
endcase
|
endfunction
|
endfunction
|
|
|
|
|
|
// Used during enque
|
function [63:0] fnOpa;
|
function [63:0] fnOpa;
|
input [7:0] opcode;
|
input [7:0] opcode;
|
input [63:0] ins;
|
input [63:0] ins;
|
input [63:0] rfo;
|
input [63:0] rfo;
|
input [63:0] epc;
|
input [63:0] epc;
|
begin
|
begin
|
`ifdef BITFIELDOPS
|
`ifdef BITFIELDOPS
|
if (opcode==`BITFIELD && ins[43:40]==4'd6) // BFINSI
|
if (opcode==`BITFIELD && ins[43:40]==`BFINSI)
|
fnOpa = ins[21:16];
|
fnOpa = ins[21:16];
|
else
|
else
|
`endif
|
`endif
|
if (opcode==`RTS) begin
|
if (opcode==`RTS) begin
|
fnOpa = (commit1_v && commit1_tgt[6:0]==7'h51) ? commit1_bus :
|
fnOpa = (commit1_v && commit1_tgt[6:0]==7'h51) ? commit1_bus :
|
| Line 2290... |
Line 2680... |
cregs[fnCar(ins)];
|
cregs[fnCar(ins)];
|
else if (opcode==`P)
|
else if (opcode==`P)
|
fnOpa = fnSpr(6'h30,epc);
|
fnOpa = fnSpr(6'h30,epc);
|
else if (opcode==`MFSPR || opcode==`MOVS)
|
else if (opcode==`MFSPR || opcode==`MOVS)
|
fnOpa = fnSpr(ins[`INSTRUCTION_RA],epc);
|
fnOpa = fnSpr(ins[`INSTRUCTION_RA],epc);
|
/*
|
|
casex(ins[21:16])
|
|
`TICK: fnOpa = tick;
|
|
`LCTR: fnOpa = lc;
|
|
`PREGS_ALL:
|
|
begin
|
|
fnOpa[3:0] = pregs[0];
|
|
fnOpa[7:4] = pregs[1];
|
|
fnOpa[11:8] = pregs[2];
|
|
fnOpa[15:12] = pregs[3];
|
|
fnOpa[19:16] = pregs[4];
|
|
fnOpa[23:20] = pregs[5];
|
|
fnOpa[27:24] = pregs[6];
|
|
fnOpa[31:28] = pregs[7];
|
|
fnOpa[35:32] = pregs[8];
|
|
fnOpa[39:36] = pregs[9];
|
|
fnOpa[43:40] = pregs[10];
|
|
fnOpa[47:44] = pregs[11];
|
|
fnOpa[51:48] = pregs[12];
|
|
fnOpa[55:52] = pregs[13];
|
|
fnOpa[59:56] = pregs[14];
|
|
fnOpa[63:60] = pregs[15];
|
|
end
|
|
`ASID: fnOpa = asid;
|
|
`SR: fnOpa = sr;
|
|
6'h1x: fnOpa = ins[19:16]==4'h0 ? 64'd0 : ins[19:16]==4'hF ? epc :
|
|
(commit0_v && commit0_tgt[6:4]==3'h5 && commit0_tgt[3:0]==ins[19:16]) ? commit0_bus :
|
|
cregs[ins[19:16]];
|
|
`ifdef SEGMENTATION
|
|
6'h2x: fnOpa =
|
|
(commit0_v && commit0_tgt[6:4]==3'h6 && commit0_tgt[3:0]==ins[18:16]) ? {commit0_bus[DBW-1:12],12'h000} :
|
|
{sregs[ins[18:16]],12'h000};
|
|
`endif
|
|
default: fnOpa = 64'h0;
|
|
endcase
|
|
*/
|
|
else
|
else
|
fnOpa = rfo;
|
fnOpa = rfo;
|
end
|
end
|
endfunction
|
endfunction
|
|
|
|
|
|
// Returns TRUE if instruction is only allowed in kernel mode.
|
function fnIsKMOnly;
|
function fnIsKMOnly;
|
input [7:0] op;
|
input [7:0] op;
|
fnIsKMOnly = op==`RTI || op==`RTE || op==`RTD || op==`TLB || op==`CLI || op==`SEI ||
|
fnIsKMOnly = op==`RTI || op==`RTE || op==`RTD || op==`TLB || op==`CLI || op==`SEI ||
|
op==`STP
|
op==`STP
|
;
|
;
|
endfunction
|
endfunction
|
|
|
|
function fnIsKMOnlyReg;
|
|
input [6:0] regx;
|
|
fnIsKMOnlyReg = regx==7'd28 || regx==7'd29 || regx==7'd30 || regx==7'd31 ||
|
|
regx==7'h5B || regx==7'h5C || regx==7'h5D || regx==7'h5E;
|
|
endfunction
|
|
|
|
// Returns TRUE if the register is automatically valid.
|
|
function fnRegIsAutoValid;
|
|
input [6:0] regno; // r0, c0, c15, tick
|
|
fnRegIsAutoValid = regno==7'h00 || regno==7'h50 || regno==7'h5F || regno==7'h72;
|
|
endfunction
|
|
|
function [15:0] fnRegstrGrp;
|
function [15:0] fnRegstrGrp;
|
input [6:0] Rn;
|
input [6:0] Rn;
|
if (!Rn[6]) begin
|
if (!Rn[6]) begin
|
fnRegstrGrp="GP";
|
fnRegstrGrp="GP";
|
end
|
end
|
| Line 2403... |
Line 2771... |
// for the moment, we look at ALU-input buffers to allow back-to-back issue of
|
// for the moment, we look at ALU-input buffers to allow back-to-back issue of
|
// dependent instructions ... we do not, however, look ahead for DRAM requests
|
// dependent instructions ... we do not, however, look ahead for DRAM requests
|
// that will become valid in the next cycle. instead, these have to propagate
|
// that will become valid in the next cycle. instead, these have to propagate
|
// their results into the IQ entry directly, at which point it becomes issue-able
|
// their results into the IQ entry directly, at which point it becomes issue-able
|
//
|
//
|
|
/*
|
always @*
|
always @*
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
iq_cmt[n] <= fnPredicate(iqentry_pred[n], iqentry_cond[n]) ||
|
iq_cmt[n] <= fnPredicate(iqentry_pred[n], iqentry_cond[n]) ||
|
(iqentry_cond[n] < 4'h2 && ({iqentry_pred[n],iqentry_cond[n]}!=8'h90));
|
(iqentry_cond[n] < 4'h2 && ({iqentry_pred[n],iqentry_cond[n]}!=8'h90));
|
|
*/
|
wire [QENTRIES-1:0] args_valid;
|
wire [QENTRIES-1:0] args_valid;
|
wire [QENTRIES-1:0] could_issue;
|
wire [QENTRIES-1:0] could_issue;
|
|
|
genvar g;
|
genvar g;
|
generate
|
generate
|
| Line 2440... |
Line 2808... |
|| (iqentry_T_s[g] == alu0_sourceid && alu0_v)
|
|| (iqentry_T_s[g] == alu0_sourceid && alu0_v)
|
|| (iqentry_T_s[g] == alu1_sourceid && alu1_v))
|
|| (iqentry_T_s[g] == alu1_sourceid && alu1_v))
|
;
|
;
|
|
|
assign could_issue[g] = iqentry_v[g] && !iqentry_done[g] && !iqentry_out[g] && args_valid[g] &&
|
assign could_issue[g] = iqentry_v[g] && !iqentry_done[g] && !iqentry_out[g] && args_valid[g] &&
|
(iqentry_mem[g] ? !iqentry_agen[g] : 1'b1);// && iq_cmt[g];
|
(iqentry_mem[g] ? !iqentry_agen[g] : 1'b1);
|
|
|
end
|
end
|
end
|
end
|
endgenerate
|
endgenerate
|
|
|
| Line 2704... |
Line 3072... |
`endif
|
`endif
|
|
|
//
|
//
|
// additional logic for handling a branch miss (STOMP logic)
|
// additional logic for handling a branch miss (STOMP logic)
|
//
|
//
|
assign iqentry_stomp[0] = branchmiss & (iqentry_v[0] && head0 != 3'd0 && (missid == 3'd7 || iqentry_stomp[7]));
|
wire [QENTRIES-1:0] alu0_issue_;
|
assign iqentry_stomp[1] = branchmiss & (iqentry_v[1] && head0 != 3'd1 && (missid == 3'd0 || iqentry_stomp[0]));
|
wire [QENTRIES-1:0] alu1_issue_;
|
assign iqentry_stomp[2] = branchmiss & (iqentry_v[2] && head0 != 3'd2 && (missid == 3'd1 || iqentry_stomp[1]));
|
wire [QENTRIES-1:0] fp0_issue_;
|
assign iqentry_stomp[3] = branchmiss & (iqentry_v[3] && head0 != 3'd3 && (missid == 3'd2 || iqentry_stomp[2]));
|
generate
|
assign iqentry_stomp[4] = branchmiss & (iqentry_v[4] && head0 != 3'd4 && (missid == 3'd3 || iqentry_stomp[3]));
|
begin : stomp_logic
|
assign iqentry_stomp[5] = branchmiss & (iqentry_v[5] && head0 != 3'd5 && (missid == 3'd4 || iqentry_stomp[4]));
|
assign iqentry_stomp[0] = branchmiss & (iqentry_v[0] && head0 != 3'd0 && ((missid == QENTRIES-1) || iqentry_stomp[QENTRIES-1]));
|
assign iqentry_stomp[6] = branchmiss & (iqentry_v[6] && head0 != 3'd6 && (missid == 3'd5 || iqentry_stomp[5]));
|
for (g = 1; g < QENTRIES; g = g + 1)
|
assign iqentry_stomp[7] = branchmiss & (iqentry_v[7] && head0 != 3'd7 && (missid == 3'd6 || iqentry_stomp[6]));
|
assign iqentry_stomp[g] = branchmiss & (iqentry_v[g] && head0 != g && ((missid == g-1) || iqentry_stomp[g-1]));
|
|
for (g = 0; g < QENTRIES; g = g + 1)
|
assign alu0_issue = (!(iqentry_v[0] && iqentry_stomp[0]) && iqentry_issue[0] && iqentry_islot[0]==2'd0) ||
|
begin
|
(!(iqentry_v[1] && iqentry_stomp[1]) && iqentry_issue[1] && iqentry_islot[1]==2'd0) ||
|
assign alu0_issue_[g] = (!(iqentry_v[g] && iqentry_stomp[g]) && iqentry_issue[g] && iqentry_islot[g]==2'd0);
|
(!(iqentry_v[2] && iqentry_stomp[2]) && iqentry_issue[2] && iqentry_islot[2]==2'd0) ||
|
assign alu1_issue_[g] = (!(iqentry_v[g] && iqentry_stomp[g]) && iqentry_issue[g] && iqentry_islot[g]==2'd1);
|
(!(iqentry_v[3] && iqentry_stomp[3]) && iqentry_issue[3] && iqentry_islot[3]==2'd0) ||
|
assign fp0_issue_[g] = (!(iqentry_v[g] && iqentry_stomp[g]) && iqentry_fpissue[g] && iqentry_islot[g]==2'd0);
|
(!(iqentry_v[4] && iqentry_stomp[4]) && iqentry_issue[4] && iqentry_islot[4]==2'd0) ||
|
end
|
(!(iqentry_v[5] && iqentry_stomp[5]) && iqentry_issue[5] && iqentry_islot[5]==2'd0) ||
|
end
|
(!(iqentry_v[6] && iqentry_stomp[6]) && iqentry_issue[6] && iqentry_islot[6]==2'd0) ||
|
endgenerate
|
(!(iqentry_v[7] && iqentry_stomp[7]) && iqentry_issue[7] && iqentry_islot[7]==2'd0)
|
|
;
|
|
|
|
assign alu1_issue = (!(iqentry_v[0] && iqentry_stomp[0]) && iqentry_issue[0] && iqentry_islot[0]==2'd1) ||
|
|
(!(iqentry_v[1] && iqentry_stomp[1]) && iqentry_issue[1] && iqentry_islot[1]==2'd1) ||
|
|
(!(iqentry_v[2] && iqentry_stomp[2]) && iqentry_issue[2] && iqentry_islot[2]==2'd1) ||
|
|
(!(iqentry_v[3] && iqentry_stomp[3]) && iqentry_issue[3] && iqentry_islot[3]==2'd1) ||
|
|
(!(iqentry_v[4] && iqentry_stomp[4]) && iqentry_issue[4] && iqentry_islot[4]==2'd1) ||
|
|
(!(iqentry_v[5] && iqentry_stomp[5]) && iqentry_issue[5] && iqentry_islot[5]==2'd1) ||
|
|
(!(iqentry_v[6] && iqentry_stomp[6]) && iqentry_issue[6] && iqentry_islot[6]==2'd1) ||
|
|
(!(iqentry_v[7] && iqentry_stomp[7]) && iqentry_issue[7] && iqentry_islot[7]==2'd1)
|
|
;
|
|
|
|
|
assign alu0_issue = |alu0_issue_;
|
|
assign alu1_issue = |alu1_issue_;
|
`ifdef FLOATING_POINT
|
`ifdef FLOATING_POINT
|
assign fp0_issue = (!(iqentry_v[0] && iqentry_stomp[0]) && iqentry_fpissue[0] && iqentry_islot[0]==2'd0) ||
|
assign fp0_issue = |fp0_issue_;
|
(!(iqentry_v[1] && iqentry_stomp[1]) && iqentry_fpissue[1] && iqentry_islot[1]==2'd0) ||
|
|
(!(iqentry_v[2] && iqentry_stomp[2]) && iqentry_fpissue[2] && iqentry_islot[2]==2'd0) ||
|
|
(!(iqentry_v[3] && iqentry_stomp[3]) && iqentry_fpissue[3] && iqentry_islot[3]==2'd0) ||
|
|
(!(iqentry_v[4] && iqentry_stomp[4]) && iqentry_fpissue[4] && iqentry_islot[4]==2'd0) ||
|
|
(!(iqentry_v[5] && iqentry_stomp[5]) && iqentry_fpissue[5] && iqentry_islot[5]==2'd0) ||
|
|
(!(iqentry_v[6] && iqentry_stomp[6]) && iqentry_fpissue[6] && iqentry_islot[6]==2'd0) ||
|
|
(!(iqentry_v[7] && iqentry_stomp[7]) && iqentry_fpissue[7] && iqentry_islot[7]==2'd0)
|
|
;
|
|
`endif
|
`endif
|
|
|
wire dcache_access_pending = dram0 == 3'd6 && (!rhit || (dram0_op==`LCL && dram0_tgt==7'd1));
|
wire dcache_access_pending = dram0 == 3'd6 && (!rhit || (dram0_op==`LCL && dram0_tgt==7'd1));
|
|
|
//
|
//
|
| Line 3108... |
Line 3458... |
: (iqentry_a1_s[n] == alu1_id) ? alu1_bus
|
: (iqentry_a1_s[n] == alu1_id) ? alu1_bus
|
: (iqentry_a1_s[n] == commit1_id) ? commit1_bus
|
: (iqentry_a1_s[n] == commit1_id) ? commit1_bus
|
: (iqentry_a1_s[n] == commit0_id) ? commit0_bus
|
: (iqentry_a1_s[n] == commit0_id) ? commit0_bus
|
: 64'hDEADDEADDEADDEAD;
|
: 64'hDEADDEADDEADDEAD;
|
|
|
|
wire [3:0] alu0nyb[0:15];
|
|
wire [3:0] alu1nyb[0:15];
|
|
wire [3:0] cmt0nyb[0:15];
|
|
wire [3:0] cmt1nyb[0:15];
|
|
|
|
generate
|
|
begin : nybs
|
|
for (g = 0; g < DBW/4; g = g + 1)
|
|
begin
|
|
assign alu0nyb[g] = alu0_bus[g*4+3:g*4];
|
|
assign alu1nyb[g] = alu1_bus[g*4+3:g*4];
|
|
assign cmt0nyb[g] = commit0_bus[g*4+3:g*4];
|
|
assign cmt1nyb[g] = commit1_bus[g*4+3:g*4];
|
|
end
|
|
end
|
|
endgenerate
|
|
|
//`include "Thor_commit_combo.v"
|
//`include "Thor_commit_combo.v"
|
// If trying to write to two branch registers at once, or trying to write
|
// If trying to write to two branch registers at once, or trying to write
|
// to two predicate registers at once, then limit the processor to single
|
// to two predicate registers at once, then limit the processor to single
|
// commit.
|
// commit.
|
// The processor does not support writing two registers in the same register
|
// The processor does not support writing two registers in the same register
|
| Line 3174... |
Line 3541... |
reg lct1;
|
reg lct1;
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (rst_i) begin
|
if (rst_i) begin
|
cpu_clk_en <= 1'b1;
|
cpu_clk_en <= 1'b1;
|
lct1 <= 1'b0;
|
lct1 <= 1'b0;
|
clk_throttle <= 16'hAAAA; // 50% power
|
clk_throttle <= STARTUP_POWER; // 50% power
|
end
|
end
|
else begin
|
else begin
|
lct1 <= ld_clk_throttle;
|
lct1 <= ld_clk_throttle;
|
clk_throttle <= {clk_throttle[14:0],clk_throttle[15]};
|
clk_throttle <= {clk_throttle[14:0],clk_throttle[15]};
|
if (ld_clk_throttle && !lct1) begin
|
if (ld_clk_throttle && !lct1) begin
|
clk_throttle <= clk_throttle_new;
|
clk_throttle <= clk_throttle_new;
|
end
|
end
|
if (nmi_i)
|
if (nmi_i)
|
clk_throttle <= 16'hAAAA;
|
clk_throttle <= STARTUP_POWER;
|
cpu_clk_en <= clk_throttle[15];
|
cpu_clk_en <= clk_throttle[15];
|
end
|
end
|
|
|
// Clock throttling bypassed for now
|
// Clock throttling bypassed for now
|
assign clk_o = clk;
|
assign clk_o = clk;
|
| Line 3210... |
Line 3577... |
alu1_ld <= 1'b0;
|
alu1_ld <= 1'b0;
|
`ifdef FLOATING_POINT
|
`ifdef FLOATING_POINT
|
fp0_ld <= 1'b0;
|
fp0_ld <= 1'b0;
|
`endif
|
`endif
|
|
|
|
mem_stringmiss <= `FALSE;
|
|
if (mem_stringmissx) begin
|
|
mem_stringmiss <= `TRUE;
|
|
dram0_op <= `NOP; // clears string miss
|
|
end
|
ic_invalidate <= `FALSE;
|
ic_invalidate <= `FALSE;
|
dc_invalidate <= `FALSE;
|
dc_invalidate <= `FALSE;
|
ic_invalidate_line <= `FALSE;
|
ic_invalidate_line <= `FALSE;
|
dc_invalidate_line <= `FALSE;
|
dc_invalidate_line <= `FALSE;
|
alu0_dataready <= `FALSE;
|
alu0_dataready <= `FALSE;
|
| Line 3329... |
Line 3701... |
rf_v[7'h5F] = `VAL; // C15 (PC)
|
rf_v[7'h5F] = `VAL; // C15 (PC)
|
rf_v[7'h72] = `VAL; // tick
|
rf_v[7'h72] = `VAL; // tick
|
queued1 = `FALSE;
|
queued1 = `FALSE;
|
queued2 = `FALSE;
|
queued2 = `FALSE;
|
allowq = `TRUE;
|
allowq = `TRUE;
|
|
dbg_stat <= dbg_stat | dbg_stat1x;
|
|
|
did_branchback <= take_branch;
|
did_branchback <= take_branch;
|
did_branchback0 <= take_branch0;
|
did_branchback0 <= take_branch0;
|
did_branchback1 <= take_branch1;
|
did_branchback1 <= take_branch1;
|
|
|
if (branchmiss) begin
|
`include "Thor_Retarget.v"
|
for (n = 1; n < NREGS; n = n + 1)
|
/*
|
if (rf_v[n] == `INV && ~livetarget[n]) begin
|
if (branchmiss) begin
|
$display("brmiss: rf_v[%d] <= VAL",n);
|
for (n = 1; n < NREGS; n = n + 1)
|
rf_v[n] = `VAL;
|
if (rf_v[n] == `INV && ~livetarget[n]) begin
|
end
|
$display("brmiss: rf_v[%d] <= VAL",n);
|
|
rf_v[n] = `VAL;
|
if (|iqentry_0_latestID[NREGS:1]) rf_source[ iqentry_tgt[0] ] <= { iqentry_mem[0], 3'd0 };
|
end
|
if (|iqentry_1_latestID[NREGS:1]) rf_source[ iqentry_tgt[1] ] <= { iqentry_mem[1], 3'd1 };
|
|
if (|iqentry_2_latestID[NREGS:1]) rf_source[ iqentry_tgt[2] ] <= { iqentry_mem[2], 3'd2 };
|
|
if (|iqentry_3_latestID[NREGS:1]) rf_source[ iqentry_tgt[3] ] <= { iqentry_mem[3], 3'd3 };
|
|
if (|iqentry_4_latestID[NREGS:1]) rf_source[ iqentry_tgt[4] ] <= { iqentry_mem[4], 3'd4 };
|
|
if (|iqentry_5_latestID[NREGS:1]) rf_source[ iqentry_tgt[5] ] <= { iqentry_mem[5], 3'd5 };
|
|
if (|iqentry_6_latestID[NREGS:1]) rf_source[ iqentry_tgt[6] ] <= { iqentry_mem[6], 3'd6 };
|
|
if (|iqentry_7_latestID[NREGS:1]) rf_source[ iqentry_tgt[7] ] <= { iqentry_mem[7], 3'd7 };
|
|
|
|
end
|
if (|iqentry_0_latestID[NREGS:1]) rf_source[ iqentry_tgt[0] ] <= { iqentry_mem[0], 3'd0 };
|
|
if (|iqentry_1_latestID[NREGS:1]) rf_source[ iqentry_tgt[1] ] <= { iqentry_mem[1], 3'd1 };
|
|
if (|iqentry_2_latestID[NREGS:1]) rf_source[ iqentry_tgt[2] ] <= { iqentry_mem[2], 3'd2 };
|
|
if (|iqentry_3_latestID[NREGS:1]) rf_source[ iqentry_tgt[3] ] <= { iqentry_mem[3], 3'd3 };
|
|
if (|iqentry_4_latestID[NREGS:1]) rf_source[ iqentry_tgt[4] ] <= { iqentry_mem[4], 3'd4 };
|
|
if (|iqentry_5_latestID[NREGS:1]) rf_source[ iqentry_tgt[5] ] <= { iqentry_mem[5], 3'd5 };
|
|
if (|iqentry_6_latestID[NREGS:1]) rf_source[ iqentry_tgt[6] ] <= { iqentry_mem[6], 3'd6 };
|
|
if (|iqentry_7_latestID[NREGS:1]) rf_source[ iqentry_tgt[7] ] <= { iqentry_mem[7], 3'd7 };
|
|
|
|
end
|
|
*/
|
if (ihit) begin
|
if (ihit) begin
|
$display("\r\n");
|
$display("\r\n");
|
$display("TIME %0d", $time);
|
$display("TIME %0d", $time);
|
end
|
end
|
|
|
| Line 3368... |
Line 3743... |
// out of r3 while writing to r3, the value read is the value written.
|
// out of r3 while writing to r3, the value read is the value written.
|
// requires BLOCKING assignments, so that we can read from rf[i] later.
|
// requires BLOCKING assignments, so that we can read from rf[i] later.
|
//
|
//
|
if (commit0_v) begin
|
if (commit0_v) begin
|
if (!rf_v[ commit0_tgt ]) begin
|
if (!rf_v[ commit0_tgt ]) begin
|
rf_v[ commit0_tgt ] = (rf_source[ commit0_tgt ] == commit0_id) || (branchmiss && iqentry_source[ commit0_id[2:0] ]);
|
rf_v[ commit0_tgt ] = (rf_source[ commit0_tgt ] == commit0_id) || ((branchmiss) && iqentry_source[ commit0_id[2:0] ]);
|
end
|
end
|
if (commit0_tgt != 7'd0) $display("r%d <- %h", commit0_tgt, commit0_bus);
|
if (commit0_tgt != 7'd0) $display("r%d <- %h", commit0_tgt, commit0_bus);
|
end
|
end
|
if (commit1_v) begin
|
if (commit1_v) begin
|
if (!rf_v[ commit1_tgt ]) begin
|
if (!rf_v[ commit1_tgt ]) begin
|
rf_v[ commit1_tgt ] = (rf_source[ commit1_tgt ] == commit1_id)|| (branchmiss && iqentry_source[ commit1_id[2:0] ]);
|
rf_v[ commit1_tgt ] = (rf_source[ commit1_tgt ] == commit1_id)|| ((branchmiss) && iqentry_source[ commit1_id[2:0] ]);
|
end
|
end
|
if (commit1_tgt != 7'd0) $display("r%d <- %h", commit1_tgt, commit1_bus);
|
if (commit1_tgt != 7'd0) $display("r%d <- %h", commit1_tgt, commit1_bus);
|
end
|
end
|
|
|
// This chunk of code has to be before the enqueue stage so that the agen bit
|
// This chunk of code has to be before the enqueue stage so that the agen bit
|
| Line 3470... |
Line 3845... |
// for us. The fetch logic needs to know how many entries were queued, this is
|
// for us. The fetch logic needs to know how many entries were queued, this is
|
// tracked in the queue stage by variables queued1,queued2,queued3. Blocking
|
// tracked in the queue stage by variables queued1,queued2,queued3. Blocking
|
// assignments are used for these vars.
|
// assignments are used for these vars.
|
//-------------------------------------------------------------------------------
|
//-------------------------------------------------------------------------------
|
//
|
//
|
|
exception_set = `FALSE;
|
queued1 = `FALSE;
|
queued1 = `FALSE;
|
queued2 = `FALSE;
|
queued2 = `FALSE;
|
allowq = `TRUE;
|
allowq = `TRUE;
|
qstomp = `FALSE;
|
qstomp = `FALSE;
|
if (branchmiss) // don't bother doing anything if there's been a branch miss
|
if (branchmiss) // don't bother doing anything if there's been a branch miss
|
| Line 3732... |
Line 4108... |
if (ihit) begin
|
if (ihit) begin
|
$display("%h %h hit0=%b hit1=%b#", spc, pc, hit0, hit1);
|
$display("%h %h hit0=%b hit1=%b#", spc, pc, hit0, hit1);
|
$display("insn=%h", insn);
|
$display("insn=%h", insn);
|
$display("%c insn0=%h insn1=%h", nmi_edge ? "*" : " ",insn0, insn1);
|
$display("%c insn0=%h insn1=%h", nmi_edge ? "*" : " ",insn0, insn1);
|
$display("takb=%d br_pc=%h #", take_branch, branch_pc);
|
$display("takb=%d br_pc=%h #", take_branch, branch_pc);
|
$display("%c%c A: %d %h %h #",
|
$display("%c%c A: %d %h %h # %d",
|
45, fetchbuf?45:62, fetchbufA_v, fetchbufA_instr, fetchbufA_pc);
|
45, fetchbuf?45:62, fetchbufA_v, fetchbufA_instr, fetchbufA_pc, fnInsnLength(fetchbufA_instr));
|
$display("%c%c B: %d %h %h #",
|
$display("%c%c B: %d %h %h # %d",
|
45, fetchbuf?45:62, fetchbufB_v, fetchbufB_instr, fetchbufB_pc);
|
45, fetchbuf?45:62, fetchbufB_v, fetchbufB_instr, fetchbufB_pc, fnInsnLength(fetchbufB_instr));
|
$display("%c%c C: %d %h %h #",
|
$display("%c%c C: %d %h %h # %d",
|
45, fetchbuf?62:45, fetchbufC_v, fetchbufC_instr, fetchbufC_pc);
|
45, fetchbuf?62:45, fetchbufC_v, fetchbufC_instr, fetchbufC_pc, fnInsnLength(fetchbufC_instr));
|
$display("%c%c D: %d %h %h #",
|
$display("%c%c D: %d %h %h # %d",
|
45, fetchbuf?62:45, fetchbufD_v, fetchbufD_instr, fetchbufD_pc);
|
45, fetchbuf?62:45, fetchbufD_v, fetchbufD_instr, fetchbufD_pc, fnInsnLength(fetchbufD_instr));
|
$display("fetchbuf=%d",fetchbuf);
|
$display("fetchbuf=%d",fetchbuf);
|
end
|
end
|
|
|
// if (ihit) begin
|
// if (ihit) begin
|
for (i=0; i<QENTRIES; i=i+1)
|
for (i=0; i<QENTRIES; i=i+1)
|
$display("%c%c %d: %c%c%c%c%c%c%c%c%c %d %c %c%h %d%s %h %h %h %c %o %h %c %o %h %c %o %h %c %o %h #",
|
$display("%c%c %d: %c%c%c%c%c%c%c%c %d %c %c%h %d%s %h %h %h %c %o %h %c %o %h %c %o %h %c %o %h #",
|
(i[2:0]==head0)?72:46, (i[2:0]==tail0)?84:46, i,
|
(i[2:0]==head0)?72:46, (i[2:0]==tail0)?84:46, i,
|
iqentry_v[i]?"v":"-", iqentry_done[i]?"d":"-",
|
iqentry_v[i]?"v":"-", iqentry_done[i]?"d":"-",
|
iqentry_cmt[i]?"c":"-", iq_cmt[i]?"C":"-",iqentry_out[i]?"o":"-", iqentry_bt[i]?"b":"-", iqentry_memissue[i]?"m":"-",
|
iqentry_cmt[i]?"c":"-", iqentry_out[i]?"o":"-", iqentry_bt[i]?"b":"-", iqentry_memissue[i]?"m":"-",
|
iqentry_agen[i]?"a":"-", iqentry_issue[i]?"i":"-",
|
iqentry_agen[i]?"a":"-", iqentry_issue[i]?"i":"-",
|
iqentry_islot[i],
|
iqentry_islot[i],
|
// ((i==0) ? iqentry_0_islot : (i==1) ? iqentry_1_islot : (i==2) ? iqentry_2_islot : (i==3) ? iqentry_3_islot :
|
// ((i==0) ? iqentry_0_islot : (i==1) ? iqentry_1_islot : (i==2) ? iqentry_2_islot : (i==3) ? iqentry_3_islot :
|
// (i==4) ? iqentry_4_islot : (i==5) ? iqentry_5_islot : (i==6) ? iqentry_6_islot : iqentry_7_islot),
|
// (i==4) ? iqentry_4_islot : (i==5) ? iqentry_5_islot : (i==6) ? iqentry_6_islot : iqentry_7_islot),
|
iqentry_stomp[i] ? "s" : "-",
|
iqentry_stomp[i] ? "s" : "-",
|
| Line 3792... |
Line 4168... |
else begin
|
else begin
|
// Note that the predicate was already evaluated to TRUE before the
|
// Note that the predicate was already evaluated to TRUE before the
|
// dram operation started.
|
// dram operation started.
|
iqentry_cmt[dram_id[2:0]] <= `TRUE;
|
iqentry_cmt[dram_id[2:0]] <= `TRUE;
|
iqentry_done[ dram_id[2:0] ] <= `TRUE;
|
iqentry_done[ dram_id[2:0] ] <= `TRUE;
|
if (iqentry_op[dram_id[2:0]]==`STS && lc==64'd0) begin
|
if ((iqentry_op[dram_id[2:0]]==`STS ||
|
|
iqentry_op[dram_id[2:0]]==`STCMP ||
|
|
iqentry_op[dram_id[2:0]]==`STMV ||
|
|
iqentry_op[dram_id[2:0]]==`STFND
|
|
) && lc==64'd0) begin
|
string_pc <= 64'd0;
|
string_pc <= 64'd0;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
| Line 3825... |
Line 4205... |
//
|
//
|
// see if anybody else wants the results ... look at lots of buses:
|
// see if anybody else wants the results ... look at lots of buses:
|
// - alu0_bus
|
// - alu0_bus
|
// - alu1_bus
|
// - alu1_bus
|
// - fp0_bus
|
// - fp0_bus
|
// - dram_bus
|
// - mem_bus
|
// - commit0_bus
|
// - commit0_bus
|
// - commit1_bus
|
// - commit1_bus
|
//
|
//
|
|
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
begin
|
begin
|
if (iqentry_p_v[n] == `INV && iqentry_p_s[n]==alu0_id && iqentry_v[n] == `VAL && alu0_v == `VAL) begin
|
if (iqentry_p_v[n] == `INV && iqentry_p_s[n]==alu0_id && iqentry_v[n] == `VAL && alu0_v == `VAL) begin
|
iqentry_pred[n] <= alu0_bus[3:0];
|
iqentry_pred[n] <= alu0nyb[iqentry_preg[n]];
|
iqentry_p_v[n] <= `VAL;
|
iqentry_p_v[n] <= `VAL;
|
end
|
end
|
if (iqentry_a1_v[n] == `INV && iqentry_a1_s[n] == alu0_id && iqentry_v[n] == `VAL && alu0_v == `VAL) begin
|
if (iqentry_a1_v[n] == `INV && iqentry_a1_s[n] == alu0_id && iqentry_v[n] == `VAL && alu0_v == `VAL) begin
|
iqentry_a1[n] <= alu0_bus;
|
iqentry_a1[n] <= alu0_bus;
|
iqentry_a1_v[n] <= `VAL;
|
iqentry_a1_v[n] <= `VAL;
|
| Line 3853... |
Line 4233... |
if (iqentry_T_v[n] == `INV && iqentry_T_s[n] == alu0_id && iqentry_v[n] == `VAL && alu0_v == `VAL) begin
|
if (iqentry_T_v[n] == `INV && iqentry_T_s[n] == alu0_id && iqentry_v[n] == `VAL && alu0_v == `VAL) begin
|
iqentry_T[n] <= alu0_bus;
|
iqentry_T[n] <= alu0_bus;
|
iqentry_T_v[n] <= `VAL;
|
iqentry_T_v[n] <= `VAL;
|
end
|
end
|
if (iqentry_p_v[n] == `INV && iqentry_p_s[n] == alu1_id && iqentry_v[n] == `VAL && alu1_v == `VAL) begin
|
if (iqentry_p_v[n] == `INV && iqentry_p_s[n] == alu1_id && iqentry_v[n] == `VAL && alu1_v == `VAL) begin
|
iqentry_pred[n] <= alu1_bus[3:0];
|
iqentry_pred[n] <= alu1nyb[iqentry_preg[n]];
|
iqentry_p_v[n] <= `VAL;
|
iqentry_p_v[n] <= `VAL;
|
end
|
end
|
if (iqentry_a1_v[n] == `INV && iqentry_a1_s[n] == alu1_id && iqentry_v[n] == `VAL && alu1_v == `VAL) begin
|
if (iqentry_a1_v[n] == `INV && iqentry_a1_s[n] == alu1_id && iqentry_v[n] == `VAL && alu1_v == `VAL) begin
|
iqentry_a1[n] <= alu1_bus;
|
iqentry_a1[n] <= alu1_bus;
|
iqentry_a1_v[n] <= `VAL;
|
iqentry_a1_v[n] <= `VAL;
|
| Line 3918... |
Line 4298... |
if (iqentry_T_v[n] == `INV && iqentry_T_s[n] == dram_id && iqentry_v[n] == `VAL && dram_v == `VAL) begin
|
if (iqentry_T_v[n] == `INV && iqentry_T_s[n] == dram_id && iqentry_v[n] == `VAL && dram_v == `VAL) begin
|
iqentry_T[n] <= dram_bus;
|
iqentry_T[n] <= dram_bus;
|
iqentry_T_v[n] <= `VAL;
|
iqentry_T_v[n] <= `VAL;
|
end
|
end
|
if (iqentry_p_v[n] == `INV && iqentry_p_s[n]==commit0_id && iqentry_v[n] == `VAL && commit0_v == `VAL) begin
|
if (iqentry_p_v[n] == `INV && iqentry_p_s[n]==commit0_id && iqentry_v[n] == `VAL && commit0_v == `VAL) begin
|
iqentry_pred[n] <= commit0_bus[3:0];
|
iqentry_pred[n] <= cmt0nyb[iqentry_preg[n]];
|
iqentry_p_v[n] <= `VAL;
|
iqentry_p_v[n] <= `VAL;
|
end
|
end
|
if (iqentry_a1_v[n] == `INV && iqentry_a1_s[n] == commit0_id && iqentry_v[n] == `VAL && commit0_v == `VAL) begin
|
if (iqentry_a1_v[n] == `INV && iqentry_a1_s[n] == commit0_id && iqentry_v[n] == `VAL && commit0_v == `VAL) begin
|
iqentry_a1[n] <= commit0_bus;
|
iqentry_a1[n] <= commit0_bus;
|
iqentry_a1_v[n] <= `VAL;
|
iqentry_a1_v[n] <= `VAL;
|
| Line 3938... |
Line 4318... |
if (iqentry_T_v[n] == `INV && iqentry_T_s[n] == commit0_id && iqentry_v[n] == `VAL && commit0_v == `VAL) begin
|
if (iqentry_T_v[n] == `INV && iqentry_T_s[n] == commit0_id && iqentry_v[n] == `VAL && commit0_v == `VAL) begin
|
iqentry_T[n] <= commit0_bus;
|
iqentry_T[n] <= commit0_bus;
|
iqentry_T_v[n] <= `VAL;
|
iqentry_T_v[n] <= `VAL;
|
end
|
end
|
if (iqentry_p_v[n] == `INV && iqentry_p_s[n] == commit1_id && iqentry_v[n] == `VAL && commit1_v == `VAL) begin
|
if (iqentry_p_v[n] == `INV && iqentry_p_s[n] == commit1_id && iqentry_v[n] == `VAL && commit1_v == `VAL) begin
|
iqentry_pred[n] <= commit1_bus[3:0];
|
iqentry_pred[n] <= cmt1nyb[iqentry_preg[n]];
|
iqentry_p_v[n] <= `VAL;
|
iqentry_p_v[n] <= `VAL;
|
end
|
end
|
if (iqentry_a1_v[n] == `INV && iqentry_a1_s[n] == commit1_id && iqentry_v[n] == `VAL && commit1_v == `VAL) begin
|
if (iqentry_a1_v[n] == `INV && iqentry_a1_s[n] == commit1_id && iqentry_v[n] == `VAL && commit1_v == `VAL) begin
|
iqentry_a1[n] <= commit1_bus;
|
iqentry_a1[n] <= commit1_bus;
|
iqentry_a1_v[n] <= `VAL;
|
iqentry_a1_v[n] <= `VAL;
|
| Line 4020... |
Line 4400... |
alu0_fn <= iqentry_fn[n];
|
alu0_fn <= iqentry_fn[n];
|
alu0_cond <= iqentry_cond[n];
|
alu0_cond <= iqentry_cond[n];
|
alu0_bt <= iqentry_bt[n];
|
alu0_bt <= iqentry_bt[n];
|
alu0_pc <= iqentry_pc[n];
|
alu0_pc <= iqentry_pc[n];
|
alu0_pred <= iqentry_p_v[n] ? iqentry_pred[n] :
|
alu0_pred <= iqentry_p_v[n] ? iqentry_pred[n] :
|
(iqentry_p_s[n] == alu0_id) ? alu0_bus[3:0] :
|
(iqentry_p_s[n] == alu0_id) ? alu0nyb[iqentry_preg[n]] :
|
(iqentry_p_s[n] == alu1_id) ? alu1_bus[3:0] : 4'h0;
|
(iqentry_p_s[n] == alu1_id) ? alu1nyb[iqentry_preg[n]] : 4'h0;
|
alu0_argA <= iqentry_a1_v[n] ? iqentry_a1[n]
|
alu0_argA <= iqentry_a1_v[n] ? iqentry_a1[n]
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a1_s[n] == alu1_id) ? alu1_bus
|
: (iqentry_a1_s[n] == alu1_id) ? alu1_bus
|
: 64'hDEADDEADDEADDEAD;
|
: 64'hDEADDEADDEADDEAD;
|
alu0_argB <= iqentry_a2_v[n] ? iqentry_a2[n]
|
alu0_argB <= iqentry_a2_v[n] ? iqentry_a2[n]
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a2_s[n] == alu1_id) ? alu1_bus
|
: (iqentry_a2_s[n] == alu1_id) ? alu1_bus
|
: 64'hDEADDEADDEADDEAD;
|
: 64'hDEADDEADDEADDEAD;
|
alu0_argC <= (iqentry_op[n]==`POP || iqentry_op[n]==`PUSH || iqentry_op[n]==`PEA) ? {sregs[3'd6],12'h000} :
|
alu0_argC <=
|
iqentry_mem[n] ? {sregs[iqentry_fn[n][5:3]],12'h000} :
|
`ifdef SEGMENTATION
|
|
`ifdef STACKOPS
|
|
(iqentry_op[n]==`POP || iqentry_op[n]==`PUSH || iqentry_op[n]==`PEA) ? {sregs[3'd6],12'h000} :
|
|
`endif
|
|
(iqentry_mem[n] && iqentry_op[n]!=`STCMP && iqentry_op[n]!=`STMV) ? {sregs[iqentry_fn[n][5:3]],12'h000} :
|
|
`endif
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a3_s[n] == alu1_id) ? alu1_bus
|
: (iqentry_a3_s[n] == alu1_id) ? alu1_bus
|
: 64'hDEADDEADDEADDEAD;
|
: 64'hDEADDEADDEADDEAD;
|
alu0_argT <= iqentry_T_v[n] ? iqentry_T[n]
|
alu0_argT <= iqentry_T_v[n] ? iqentry_T[n]
|
| Line 4053... |
Line 4438... |
alu1_fn <= iqentry_fn[n];
|
alu1_fn <= iqentry_fn[n];
|
alu1_cond <= iqentry_cond[n];
|
alu1_cond <= iqentry_cond[n];
|
alu1_bt <= iqentry_bt[n];
|
alu1_bt <= iqentry_bt[n];
|
alu1_pc <= iqentry_pc[n];
|
alu1_pc <= iqentry_pc[n];
|
alu1_pred <= iqentry_p_v[n] ? iqentry_pred[n] :
|
alu1_pred <= iqentry_p_v[n] ? iqentry_pred[n] :
|
(iqentry_p_s[n] == alu0_id) ? alu0_bus[3:0] :
|
(iqentry_p_s[n] == alu0_id) ? alu0nyb[iqentry_preg[n]] :
|
(iqentry_p_s[n] == alu1_id) ? alu1_bus[3:0] : 4'h0;
|
(iqentry_p_s[n] == alu1_id) ? alu1nyb[iqentry_preg[n]] : 4'h0;
|
alu1_argA <= iqentry_a1_v[n] ? iqentry_a1[n]
|
alu1_argA <= iqentry_a1_v[n] ? iqentry_a1[n]
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a1_s[n] == alu1_id) ? alu1_bus
|
: (iqentry_a1_s[n] == alu1_id) ? alu1_bus
|
: 64'hDEADDEADDEADDEAD;
|
: 64'hDEADDEADDEADDEAD;
|
alu1_argB <= iqentry_a2_v[n] ? iqentry_a2[n]
|
alu1_argB <= iqentry_a2_v[n] ? iqentry_a2[n]
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a2_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a2_s[n] == alu1_id) ? alu1_bus
|
: (iqentry_a2_s[n] == alu1_id) ? alu1_bus
|
: 64'hDEADDEADDEADDEAD;
|
: 64'hDEADDEADDEADDEAD;
|
alu1_argC <= (iqentry_op[n]==`POP || iqentry_op[n]==`PUSH || iqentry_op[n]==`PEA) ? {sregs[3'd6],12'h000} :
|
alu1_argC <=
|
iqentry_mem[n] ? {sregs[iqentry_fn[n][5:3]],12'h000} :
|
`ifdef SEGMENTATION
|
|
`ifdef STACKOPS
|
|
(iqentry_op[n]==`POP || iqentry_op[n]==`PUSH || iqentry_op[n]==`PEA) ? {sregs[3'd6],12'h000} :
|
|
`endif
|
|
(iqentry_mem[n] && iqentry_op[n]!=`STCMP && iqentry_op[n]!=`STMV)? {sregs[iqentry_fn[n][5:3]],12'h000} :
|
|
`endif
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
iqentry_a3_v[n] ? iqentry_a3[n]
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a3_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a3_s[n] == alu1_id) ? alu1_bus
|
: (iqentry_a3_s[n] == alu1_id) ? alu1_bus
|
: 64'hDEADDEADDEADDEAD;
|
: 64'hDEADDEADDEADDEAD;
|
alu1_argT <= iqentry_T_v[n] ? iqentry_T[n]
|
alu1_argT <= iqentry_T_v[n] ? iqentry_T[n]
|
| Line 4102... |
Line 4492... |
fp0_sourceid <= n[3:0];
|
fp0_sourceid <= n[3:0];
|
fp0_op <= iqentry_op[n];
|
fp0_op <= iqentry_op[n];
|
fp0_fn <= iqentry_fn[n];
|
fp0_fn <= iqentry_fn[n];
|
fp0_cond <= iqentry_cond[n];
|
fp0_cond <= iqentry_cond[n];
|
fp0_pred <= iqentry_p_v[n] ? iqentry_pred[n] :
|
fp0_pred <= iqentry_p_v[n] ? iqentry_pred[n] :
|
(iqentry_p_s[n] == alu0_id) ? alu0_bus[3:0] :
|
(iqentry_p_s[n] == alu0_id) ? alu0nyb[iqentry_preg[n]] :
|
(iqentry_p_s[n] == alu1_id) ? alu1_bus[3:0] : 4'h0;
|
(iqentry_p_s[n] == alu1_id) ? alu1nyb[iqentry_preg[n]] : 4'h0;
|
fp0_argA <= iqentry_a1_v[n] ? iqentry_a1[n]
|
fp0_argA <= iqentry_a1_v[n] ? iqentry_a1[n]
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a1_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_a1_s[n] == alu1_id) ? alu1_bus
|
: (iqentry_a1_s[n] == alu1_id) ? alu1_bus
|
: 64'hDEADDEADDEADDEAD;
|
: 64'hDEADDEADDEADDEAD;
|
fp0_argB <= iqentry_a2_v[n] ? iqentry_a2[n]
|
fp0_argB <= iqentry_a2_v[n] ? iqentry_a2[n]
|
| Line 4160... |
Line 4550... |
tlb_state <= 3'd0;
|
tlb_state <= 3'd0;
|
end
|
end
|
|
|
case(dram0)
|
case(dram0)
|
// The first state is to translate the virtual to physical address.
|
// The first state is to translate the virtual to physical address.
|
|
// Also a good spot to check for debug match and segment limit violation.
|
3'd1:
|
3'd1:
|
begin
|
begin
|
$display("0MEM %c:%h %h cycle started",fnIsLoad(dram0_op)?"L" : "S", dram0_addr, dram0_data);
|
$display("0MEM %c:%h %h cycle started",fnIsStore(dram0_op)?"S" : "L", dram0_addr, dram0_data);
|
if (dbg_lmatch|dbg_smatch) begin
|
if (dbg_lmatch|dbg_smatch) begin
|
dram_v <= `TRUE;
|
dram_v <= `TRUE;
|
dram_id <= dram0_id;
|
dram_id <= dram0_id;
|
dram_tgt <= dram0_tgt;
|
dram_tgt <= dram0_tgt;
|
dram_exc <= `EXC_DBG;
|
dram_exc <= `EXC_DBG;
|
| Line 4258... |
Line 4649... |
dram0 <= 3'd7;
|
dram0 <= 3'd7;
|
case(dram0_op)
|
case(dram0_op)
|
`ifdef STRINGOPS
|
`ifdef STRINGOPS
|
`STS:
|
`STS:
|
if (lc != 0 && !int_pending) begin
|
if (lc != 0 && !int_pending) begin
|
dram0_owns_bus <= `TRUE;
|
dram0_addr <= dram0_addr + fnIndexAmt(dram0_fn);
|
dram0_addr <= dram0_addr +
|
|
(dram0_fn[2:0]==3'd0 ? 64'd1 :
|
|
dram0_fn[2:0]==3'd1 ? 64'd2 :
|
|
dram0_fn[2:0]==3'd2 ? 64'd4 :
|
|
64'd8);
|
|
lc <= lc - 64'd1;
|
lc <= lc - 64'd1;
|
dram0 <= 3'd1;
|
dram0 <= 3'd1;
|
dram_bus <= dram0_addr +
|
dram_bus <= dram0_addr + fnIndexAmt(dram0_fn);
|
(dram0_fn[2:0]==3'd0 ? 64'd1 :
|
|
dram0_fn[2:0]==3'd1 ? 64'd2 :
|
|
dram0_fn[2:0]==3'd2 ? 64'd4 :
|
|
64'd8);
|
|
end
|
end
|
else begin
|
else begin
|
dram_bus <= dram0_addr +
|
dram_bus <= dram0_addr + fnIndexAmt(dram0_fn) - dram0_seg;
|
(dram0_fn[2:0]==3'd0 ? 64'd1 :
|
|
dram0_fn[2:0]==3'd1 ? 64'd2 :
|
|
dram0_fn[2:0]==3'd2 ? 64'd4 :
|
|
64'd8) - dram0_seg;
|
|
dram_v <= `VAL;
|
dram_v <= `VAL;
|
end
|
end
|
`STMV,`STCMP:
|
`STMV,`STCMP:
|
|
begin
|
|
dram_bus <= index;
|
if (lc != 0 && !(int_pending && stmv_flag)) begin
|
if (lc != 0 && !(int_pending && stmv_flag)) begin
|
dram0 <= 3'd1;
|
dram0 <= 3'd1;
|
dram0_owns_bus <= `TRUE;
|
dram0_owns_bus <= `TRUE;
|
if (stmv_flag) begin
|
if (stmv_flag) begin
|
dram0_addr <= src_addr + index;
|
dram0_addr <= src_addr + index;
|
if (dram0_op==`STCMP) begin
|
if (dram0_op==`STCMP) begin
|
if (dram0_data != fnDatai(dram0_op,dram0_fn,dat_i,rsel)) begin
|
if (dram0_data != fnDatai(dram0_op,dram0_fn,dat_i,rsel)) begin
|
lc <= 64'd0;
|
lc <= 64'd0;
|
dram0 <= 3'd7;
|
dram0 <= 3'd7;
|
dram_v <= `VAL;
|
dram_v <= `VAL;
|
dram_bus <= index;
|
|
end
|
end
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
dram0_addr <= dst_addr + index;
|
dram0_addr <= dst_addr + index;
|
| Line 4304... |
Line 4683... |
if (!stmv_flag)
|
if (!stmv_flag)
|
inc_index(dram0_fn);
|
inc_index(dram0_fn);
|
stmv_flag <= ~stmv_flag;
|
stmv_flag <= ~stmv_flag;
|
end
|
end
|
else begin
|
else begin
|
dram_bus <= index;
|
|
dram_v <= `VAL;
|
dram_v <= `VAL;
|
end
|
end
|
|
end
|
`STFND:
|
`STFND:
|
if (lc != 0 && !int_pending) begin
|
if (lc != 0 && !int_pending) begin
|
dram0_addr <= src_addr + index;
|
dram0_addr <= src_addr + index;
|
inc_index(dram0_fn);
|
inc_index(dram0_fn);
|
if (dram0_data == dram_bus) begin
|
if (dram0_data == fnDatai(dram0_op,dram0_fn,dat_i,rsel)) begin
|
lc <= 64'd0;
|
lc <= 64'd0;
|
dram0 <= 3'd7;
|
|
dram_v <= `VAL;
|
dram_v <= `VAL;
|
dram_bus <= index;
|
dram_bus <= index;
|
end
|
end
|
else
|
else
|
dram0 <= 3'd1;
|
dram0 <= 3'd1;
|
| Line 4332... |
Line 4710... |
$display("CAS match");
|
$display("CAS match");
|
dram0_owns_bus <= `TRUE;
|
dram0_owns_bus <= `TRUE;
|
cyc_o <= 1'b1; // hold onto cyc_o
|
cyc_o <= 1'b1; // hold onto cyc_o
|
dram0 <= dram0 + 3'd1;
|
dram0 <= dram0 + 3'd1;
|
end
|
end
|
else
|
else begin
|
dram_v <= `VAL;
|
dram_v <= `VAL;
|
|
dram0 <= 3'd0;
|
|
end
|
`INC:
|
`INC:
|
begin
|
begin
|
if (stmv_flag) begin
|
if (stmv_flag) begin
|
dram_v <= `VAL;
|
dram_v <= `VAL;
|
|
dram0 <= 3'd0;
|
end
|
end
|
else begin
|
else begin
|
dram0_data <= fnDatai(dram0_op,dram0_fn,dat_i,rsel);
|
dram0_data <= fnDatai(dram0_op,dram0_fn,dat_i,rsel);
|
stmv_flag <= ~stmv_flag;
|
stmv_flag <= ~stmv_flag;
|
dram0 <= 3'd2;
|
dram0 <= 3'd1;
|
end
|
end
|
end
|
end
|
|
`NOP:
|
|
begin
|
|
dram_v <= `VAL;
|
|
dram0 <= 3'd0;
|
|
end
|
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
|
|
// State 4:
|
// State 4:
|
| Line 4365... |
Line 4751... |
|
|
// State 5:
|
// State 5:
|
// Wait for a memory ack for the second bus transaction of a CAS
|
// Wait for a memory ack for the second bus transaction of a CAS
|
//
|
//
|
3'd5:
|
3'd5:
|
|
begin
|
|
dram_id <= dram0_id;
|
|
dram_tgt <= dram0_tgt;
|
if (ack_i|err_i) begin
|
if (ack_i|err_i) begin
|
$display("MEM ack2");
|
$display("MEM ack2");
|
dram_v <= `VAL;
|
dram_v <= `VAL;
|
dram_id <= dram0_id;
|
|
dram_tgt <= dram0_tgt;
|
|
dram_exc <= (err_i & dram0_tgt!=7'd0) ? `EXC_DBE : `EXC_NONE;
|
dram_exc <= (err_i & dram0_tgt!=7'd0) ? `EXC_DBE : `EXC_NONE;
|
dram0_owns_bus <= `FALSE;
|
dram0_owns_bus <= `FALSE;
|
wb_nack();
|
wb_nack();
|
lock_o <= 1'b0;
|
lock_o <= 1'b0;
|
dram0 <= 3'd7;
|
dram0 <= 3'd7;
|
end
|
end
|
|
end
|
|
|
// State 6:
|
// State 6:
|
// Wait for a data cache read hit
|
// Wait for a data cache read hit
|
3'd6:
|
3'd6:
|
if (rhit && dram0_op!=`LCL) begin
|
if (rhit && dram0_op!=`LCL) begin
|
| Line 4390... |
Line 4778... |
`STMV:
|
`STMV:
|
begin
|
begin
|
stmv_flag <= `TRUE;
|
stmv_flag <= `TRUE;
|
dram0_addr <= dst_addr + index;
|
dram0_addr <= dst_addr + index;
|
dram0_data <= fnDatai(dram0_op,dram0_fn,cdat,rsel);
|
dram0_data <= fnDatai(dram0_op,dram0_fn,cdat,rsel);
|
dram0 <= 3'd2;
|
dram0 <= 3'd1;
|
end
|
end
|
`STCMP:
|
`STCMP:
|
|
begin
|
|
dram_bus <= index;
|
|
dram_id <= dram0_id;
|
|
dram_tgt <= dram0_tgt;
|
if (lc != 0 && !int_pending && stmv_flag) begin
|
if (lc != 0 && !int_pending && stmv_flag) begin
|
dram0_addr <= src_addr + index;
|
dram0_addr <= src_addr + index;
|
stmv_flag <= ~stmv_flag;
|
stmv_flag <= ~stmv_flag;
|
if (dram0_data != dram_bus) begin
|
$display("*****************************");
|
|
$display("STCMP READ2:%H",fnDatai(dram0_op,dram0_fn,cdat,rsel));
|
|
$display("*****************************");
|
|
if (dram0_data != fnDatai(dram0_op,dram0_fn,cdat,rsel)) begin
|
lc <= 64'd0;
|
lc <= 64'd0;
|
dram0 <= 3'd7;
|
dram0 <= 3'd7;
|
dram_v <= `VAL;
|
dram_v <= `VAL;
|
dram_bus <= index;
|
|
dram_id <= dram0_id;
|
|
dram_tgt <= dram0_tgt;
|
|
end
|
end
|
end
|
end
|
else if (!stmv_flag) begin
|
else if (!stmv_flag) begin
|
stmv_flag <= ~stmv_flag;
|
stmv_flag <= ~stmv_flag;
|
dram0_addr <= dst_addr + index;
|
dram0_addr <= dst_addr + index;
|
dram0_data <= fnDatai(dram0_op,dram0_fn,cdat,rsel);
|
dram0_data <= fnDatai(dram0_op,dram0_fn,cdat,rsel);
|
dram0 <= 3'd2;
|
$display("*****************************");
|
|
$display("STCMP READ1:%H",fnDatai(dram0_op,dram0_fn,cdat,rsel));
|
|
$display("*****************************");
|
|
dram0 <= 3'd1;
|
inc_index(dram0_fn);
|
inc_index(dram0_fn);
|
end
|
end
|
else begin
|
else begin
|
dram_id <= dram0_id;
|
|
dram_tgt <= dram0_tgt;
|
|
dram_bus <= index;
|
|
dram_v <= `VAL;
|
dram_v <= `VAL;
|
dram0 <= 3'd7;
|
dram0 <= 3'd7;
|
end
|
end
|
|
end
|
`STFND:
|
`STFND:
|
|
begin
|
|
dram_id <= dram0_id;
|
|
dram_tgt <= dram0_tgt;
|
|
dram_bus <= index;
|
if (lc != 0 && !int_pending) begin
|
if (lc != 0 && !int_pending) begin
|
|
dram0 <= 3'd1;
|
dram0_addr <= src_addr + index;
|
dram0_addr <= src_addr + index;
|
inc_index(dram0_fn);
|
inc_index(dram0_fn);
|
if (dram0_data == dram_bus) begin
|
if (dram0_data == fnDatai(dram0_op,dram0_fn,cdat,rsel)) begin
|
lc <= 64'd0;
|
lc <= 64'd0;
|
dram_id <= dram0_id;
|
|
dram_tgt <= dram0_tgt;
|
|
dram0 <= 3'd7;
|
dram0 <= 3'd7;
|
dram_v <= `VAL;
|
dram_v <= `VAL;
|
dram_bus <= index;
|
|
end
|
end
|
end
|
end
|
else begin
|
else begin
|
dram_id <= dram0_id;
|
|
dram_tgt <= dram0_tgt;
|
|
dram_bus <= index;
|
|
dram_v <= `VAL;
|
dram_v <= `VAL;
|
dram0 <= 3'd7;
|
dram0 <= 3'd7;
|
end
|
end
|
|
end
|
`endif
|
`endif
|
`INC:
|
`INC:
|
begin
|
begin
|
dram0_data <= fnDatai(dram0_op,dram0_fn,cdat,rsel);
|
dram0_data <= fnDatai(dram0_op,dram0_fn,cdat,rsel);
|
stmv_flag <= `TRUE;
|
stmv_flag <= `TRUE;
|
dram0 <= 3'd2;
|
dram0 <= 3'd1;
|
|
end
|
|
// Set to NOP on a string miss
|
|
`NOP: begin
|
|
dram_v <= `VAL;
|
|
dram0 <= 3'd0;
|
end
|
end
|
default: begin
|
default: begin
|
$display("Read hit [%h]",dram0_addr);
|
$display("Read hit [%h]",dram0_addr);
|
dram_v <= `TRUE;
|
dram_v <= `TRUE;
|
dram_id <= dram0_id;
|
dram_id <= dram0_id;
|
| Line 4458... |
Line 4856... |
dram0 <= 3'd0;
|
dram0 <= 3'd0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
3'd7:
|
3'd7:
|
|
begin
|
dram0 <= 3'd0;
|
dram0 <= 3'd0;
|
|
end
|
|
default: dram0 <= 3'd0;
|
endcase
|
endcase
|
|
|
//
|
//
|
// determine if the instructions ready to issue can, in fact, issue.
|
// determine if the instructions ready to issue can, in fact, issue.
|
// "ready" means that the instruction has valid operands but has not gone yet
|
// "ready" means that the instruction has valid operands but has not gone yet
|
| Line 4500... |
Line 4901... |
// for rf_v[].
|
// for rf_v[].
|
//
|
//
|
for (n = 0; n < QENTRIES; n = n + 1)
|
for (n = 0; n < QENTRIES; n = n + 1)
|
if (!iqentry_stomp[n] && iqentry_memissue[n] && iqentry_agen[n] && iqentry_op[n]==`TLB && !iqentry_out[n]) begin
|
if (!iqentry_stomp[n] && iqentry_memissue[n] && iqentry_agen[n] && iqentry_op[n]==`TLB && !iqentry_out[n]) begin
|
$display("TLB issue");
|
$display("TLB issue");
|
if (!iq_cmt[n]) begin
|
if (!iqentry_cmt[n]) begin
|
iqentry_cmt[n] <= `FALSE;
|
|
iqentry_done[n] <= `TRUE;
|
iqentry_done[n] <= `TRUE;
|
iqentry_out[n] <= `FALSE;
|
iqentry_out[n] <= `FALSE;
|
iqentry_agen[n] <= `FALSE;
|
iqentry_agen[n] <= `FALSE;
|
iqentry_res[n] <= iqentry_T_v[n] ? iqentry_T[n]
|
iqentry_res[n] <= iqentry_T_v[n] ? iqentry_T[n]
|
: (iqentry_T_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_T_s[n] == alu0_id) ? alu0_bus
|
| Line 4521... |
Line 4921... |
tlb_data <= iqentry_a1[n];
|
tlb_data <= iqentry_a1[n];
|
iqentry_out[n] <= `TRUE;
|
iqentry_out[n] <= `TRUE;
|
end
|
end
|
end
|
end
|
else if (!iqentry_stomp[n] && iqentry_memissue[n] && iqentry_agen[n] && !iqentry_out[n]) begin
|
else if (!iqentry_stomp[n] && iqentry_memissue[n] && iqentry_agen[n] && !iqentry_out[n]) begin
|
if (!iq_cmt[n]) begin
|
if (!iqentry_cmt[n]) begin
|
iqentry_cmt[n] <= `FALSE;
|
|
iqentry_done[n] <= `TRUE;
|
iqentry_done[n] <= `TRUE;
|
iqentry_out[n] <= `FALSE;
|
iqentry_out[n] <= `FALSE;
|
iqentry_agen[n] <= `FALSE;
|
iqentry_agen[n] <= `FALSE;
|
iqentry_res[n] <= iqentry_T_v[n] ? iqentry_T[n]
|
iqentry_res[n] <= iqentry_T_v[n] ? iqentry_T[n]
|
: (iqentry_T_s[n] == alu0_id) ? alu0_bus
|
: (iqentry_T_s[n] == alu0_id) ? alu0_bus
|
| Line 4538... |
Line 4937... |
string_pc <= iqentry_pc[n];
|
string_pc <= iqentry_pc[n];
|
$display("issued memory cycle");
|
$display("issued memory cycle");
|
if (dram0 == `DRAMSLOT_AVAIL) begin
|
if (dram0 == `DRAMSLOT_AVAIL) begin
|
dram0 <= 3'd1;
|
dram0 <= 3'd1;
|
dram0_id <= { 1'b1, n[2:0] };
|
dram0_id <= { 1'b1, n[2:0] };
|
|
dram0_misspc <= iqentry_pc[n];
|
dram0_op <= iqentry_op[n];
|
dram0_op <= iqentry_op[n];
|
dram0_fn <= iqentry_fn[n];
|
dram0_fn <= iqentry_fn[n];
|
dram0_tgt <= iqentry_tgt[n];
|
dram0_tgt <= iqentry_tgt[n];
|
dram0_data <= (fnIsIndexed(iqentry_op[n]) || iqentry_op[n]==`CAS) ? iqentry_a3[n] :
|
dram0_data <= (fnIsIndexed(iqentry_op[n]) || iqentry_op[n]==`CAS) ? iqentry_a3[n] :
|
`ifdef STACKOPS
|
`ifdef STACKOPS
|
iqentry_op[n]==`PEA ? iqentry_a2[n] + iqentry_a0[n] :
|
iqentry_op[n]==`PEA ? iqentry_a2[n] + iqentry_a0[n] :
|
`endif
|
`endif
|
iqentry_a2[n];
|
iqentry_a2[n];
|
dram0_datacmp <= iqentry_a2[n];
|
dram0_datacmp <= iqentry_a2[n];
|
`ifdef SEGMENTATION
|
`ifdef SEGMENTATION
|
|
if (iqentry_op[n]==`STCMP || iqentry_op[n]==`STMV)
|
|
dram0_addr <= iqentry_a1[n] + {sregs[iqentry_fn[n][5:3]],12'h000};
|
|
else
|
dram0_addr <= iqentry_a1[n];
|
dram0_addr <= iqentry_a1[n];
|
dram0_seg <= {sregs[iqentry_fn[n][5:3]],12'h000};
|
dram0_seg <= {sregs[iqentry_fn[n][5:3]],12'h000};
|
dram0_lmt <= sregs[iqentry_fn[n][5:3]] + sregs_lmt[iqentry_fn[n][5:3]];
|
dram0_lmt <= sregs[iqentry_fn[n][5:3]] + sregs_lmt[iqentry_fn[n][5:3]];
|
// dram0_exc <= (iqentry_a1[n][ABW-1:12] >= sregs_lmt[iqentry_fn[n][5:3]]) ? `EXC_SEGV : `EXC_NONE;
|
// dram0_exc <= (iqentry_a1[n][ABW-1:12] >= sregs_lmt[iqentry_fn[n][5:3]]) ? `EXC_SEGV : `EXC_NONE;
|
`ifdef STRINGOPS
|
`ifdef STRINGOPS
|
| Line 4564... |
Line 4967... |
src_addr <= iqentry_a1[n];
|
src_addr <= iqentry_a1[n];
|
dst_addr <= iqentry_a2[n];
|
dst_addr <= iqentry_a2[n];
|
`endif
|
`endif
|
`endif
|
`endif
|
stmv_flag <= `FALSE;
|
stmv_flag <= `FALSE;
|
index <= iqentry_op[n]==`INC ? iqentry_a2[n] : iqentry_a3[n];
|
index <= iqentry_op[n]==`STS ? fnIndexAmt(iqentry_fn[n]) : iqentry_op[n]==`INC ? iqentry_a2[n] : iqentry_a3[n];
|
iqentry_out[n] <= `TRUE;
|
iqentry_out[n] <= `TRUE;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
| Line 4610... |
Line 5013... |
// $display("vp=%h G=%b",utlb1.TLBVirtPage[i],utlb1.TLBG[i]);
|
// $display("vp=%h G=%b",utlb1.TLBVirtPage[i],utlb1.TLBG[i]);
|
//`include "Thor_commit.v"
|
//`include "Thor_commit.v"
|
// It didn't work in simulation when the following was declared under an
|
// It didn't work in simulation when the following was declared under an
|
// independant always clk block
|
// independant always clk block
|
//
|
//
|
commit_spr(commit0_v,commit0_tgt,commit0_bus);
|
commit_spr(commit0_v,commit0_tgt,commit0_bus,0);
|
commit_spr(commit1_v,commit1_tgt,commit1_bus);
|
commit_spr(commit1_v,commit1_tgt,commit1_bus,1);
|
|
|
// When the INT instruction commits set the hardware interrupt status to disable further interrupts.
|
// When the INT instruction commits set the hardware interrupt status to disable further interrupts.
|
if (int_commit)
|
if (int_commit)
|
begin
|
begin
|
$display("*********************");
|
$display("*********************");
|
| Line 4996... |
Line 5399... |
|
|
task commit_spr;
|
task commit_spr;
|
input commit_v;
|
input commit_v;
|
input [6:0] commit_tgt;
|
input [6:0] commit_tgt;
|
input [DBW-1:0] commit_bus;
|
input [DBW-1:0] commit_bus;
|
|
input which;
|
begin
|
begin
|
if (commit_v && commit_tgt[6]) begin
|
if (commit_v && commit_tgt[6]) begin
|
casex(commit_tgt[5:0])
|
casex(commit_tgt[5:0])
|
6'b00xxxx: begin
|
6'b00xxxx: begin
|
pregs[commit_tgt[3:0]] <= commit_bus[3:0];
|
pregs[commit_tgt[3:0]] <= which ? cmt1nyb[commit_tgt[3:0]] : cmt0nyb[commit_tgt[3:0]];//commit_bus[3:0];
|
$display("pregs[%d]<=%h", commit_tgt[3:0], commit_bus[3:0]);
|
$display("pregs[%d]<=%h", commit_tgt[3:0], commit_bus[3:0]);
|
// $stop;
|
// $stop;
|
end
|
end
|
6'b01xxxx: begin
|
6'b01xxxx: begin
|
cregs[commit_tgt[3:0]] <= commit_bus;
|
cregs[commit_tgt[3:0]] <= commit_bus;
|
| Line 5053... |
Line 5457... |
6'd0: dbg_adr0 <= commit_bus;
|
6'd0: dbg_adr0 <= commit_bus;
|
6'd1: dbg_adr1 <= commit_bus;
|
6'd1: dbg_adr1 <= commit_bus;
|
6'd2: dbg_adr2 <= commit_bus;
|
6'd2: dbg_adr2 <= commit_bus;
|
6'd3: dbg_adr3 <= commit_bus;
|
6'd3: dbg_adr3 <= commit_bus;
|
6'd4: dbg_ctrl <= commit_bus;
|
6'd4: dbg_ctrl <= commit_bus;
|
|
6'd5: dbg_stat <= commit_bus;
|
endcase
|
endcase
|
6'b111111:
|
6'b111111:
|
begin
|
begin
|
ld_clk_throttle <= `TRUE;
|
ld_clk_throttle <= `TRUE;
|
clk_throttle_new <= commit_bus[15:0];
|
clk_throttle_new <= commit_bus[15:0];
|
| Line 5065... |
Line 5470... |
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
// For string memory operations.
|
// For string memory operations.
|
|
// Indexing amount, should synth to a ROM.
|
//
|
//
|
task inc_index;
|
function [63:0] fnIndexAmt;
|
input [5:0] fn;
|
input [5:0] fn;
|
begin
|
begin
|
case(fn[2:0])
|
case(fn[2:0])
|
3'd0: index <= index + 64'd1;
|
3'd0: fnIndexAmt = 64'd1;
|
3'd1: index <= index + 64'd2;
|
3'd1: fnIndexAmt = 64'd2;
|
3'd2: index <= index + 64'd4;
|
3'd2: fnIndexAmt = 64'd4;
|
3'd3: index <= index + 64'd8;
|
3'd3: fnIndexAmt = 64'd8;
|
3'd4: index <= index - 64'd1;
|
3'd4: fnIndexAmt = 64'd1;
|
3'd5: index <= index - 64'd2;
|
3'd5: fnIndexAmt = 64'd2;
|
3'd6: index <= index - 64'd4;
|
3'd6: fnIndexAmt = 64'd4;
|
3'd7: index <= index - 64'd8;
|
3'd7: fnIndexAmt = 64'd8;
|
endcase
|
endcase
|
|
end
|
|
endfunction
|
|
|
|
|
|
// For string memory operations.
|
|
//
|
|
task inc_index;
|
|
input [5:0] fn;
|
|
begin
|
|
index <= index + fnIndexAmt(fn);
|
lc <= lc - 64'd1;
|
lc <= lc - 64'd1;
|
end
|
end
|
endtask
|
endtask
|
|
|
function [DBW-1:0] fnSpr;
|
function [DBW-1:0] fnSpr;
|
| Line 5090... |
Line 5506... |
input [63:0] epc;
|
input [63:0] epc;
|
begin
|
begin
|
// Read from the special registers unless overridden by the
|
// Read from the special registers unless overridden by the
|
// value on the commit bus.
|
// value on the commit bus.
|
casex(regno)
|
casex(regno)
|
6'b00xxxx: fnSpr = pregs[regno[3:0]];
|
6'b00xxxx: fnSpr = {DBW/4{pregs[regno[3:0]]}};
|
6'b01xxxx: fnSpr = cregs[regno[3:0]];
|
6'b01xxxx: fnSpr = cregs[regno[3:0]];
|
|
`ifdef SEGMENTATION
|
6'b100xxx: fnSpr = {sregs[regno[2:0]],12'h000};
|
6'b100xxx: fnSpr = {sregs[regno[2:0]],12'h000};
|
6'b101xxx: fnSpr = {sregs_lmt[regno[2:0]],12'h000};
|
6'b101xxx: fnSpr = {sregs_lmt[regno[2:0]],12'h000};
|
|
`endif
|
6'b110000: if (DBW==64)
|
6'b110000: if (DBW==64)
|
fnSpr = {pregs[15],pregs[14],pregs[13],pregs[12],
|
fnSpr = {pregs[15],pregs[14],pregs[13],pregs[12],
|
pregs[11],pregs[10],pregs[9],pregs[8],
|
pregs[11],pregs[10],pregs[9],pregs[8],
|
pregs[7],pregs[6],pregs[5],pregs[4],
|
pregs[7],pregs[6],pregs[5],pregs[4],
|
pregs[3],pregs[2],pregs[1],pregs[0]};
|
pregs[3],pregs[2],pregs[1],pregs[0]};
|
| Line 5183... |
Line 5601... |
default: ;
|
default: ;
|
endcase
|
endcase
|
end
|
end
|
endtask
|
endtask
|
|
|
|
// The exception_set var is used to reduce the number of logic levels. Rather
|
|
// than having an if/elseif tree for all the exceptional conditions that are
|
|
// trapped. The exception_set var tracks these excaptions and reduces the
|
|
// tree to a single if.
|
task enque0a;
|
task enque0a;
|
input [2:0] tail;
|
input [2:0] tail;
|
input [2:0] inc;
|
input [2:0] inc;
|
input unlink;
|
input unlink;
|
begin
|
begin
|
|
`ifdef SEGMENTATION
|
// If segment limit exceeded and not in the non-segmented area.
|
// If segment limit exceeded and not in the non-segmented area.
|
if (fetchbuf0_pc >= {sregs_lmt[7],12'h000} && fetchbuf0_pc[ABW-1:ABW-4]!=4'hF)
|
if (fetchbuf0_pc >= {sregs_lmt[7],12'h000} && fetchbuf0_pc[ABW-1:ABW-4]!=4'hF)
|
set_exception(tail,8'd244);
|
set_exception(tail,8'd244);
|
else begin
|
`endif
|
|
// If targeting a kernel mode register and not in kernel mode.
|
|
// But okay if it is an SYS or INT instruction.
|
|
if (fnIsKMOnlyReg(Rt0) && !km && !(opcode0==`SYS || opcode0==`INT))
|
|
set_exception(tail,8'd245);
|
|
// If attempting to use an undefined instruction
|
|
`ifdef TRAP_ILLEGALOPS
|
|
if (fnIsIllegal(opcode0,opcode0==`MLO ? rfoc0[5:0] : fnFunc(fetchbuf0_instr)))
|
|
set_exception(tail,8'd250);
|
|
`endif
|
`ifdef DEBUG_LOGIC
|
`ifdef DEBUG_LOGIC
|
if (dbg_ctrl[0] && dbg_ctrl[17:16]==2'b00 && fetchbuf0_pc==dbg_adr0)
|
if (dbg_ctrl[0] && dbg_ctrl[17:16]==2'b00 && fetchbuf0_pc==dbg_adr0)
|
dbg_imatchA0 = `TRUE;
|
dbg_imatchA0 = `TRUE;
|
if (dbg_ctrl[1] && dbg_ctrl[21:20]==2'b00 && fetchbuf0_pc==dbg_adr1)
|
if (dbg_ctrl[1] && dbg_ctrl[21:20]==2'b00 && fetchbuf0_pc==dbg_adr1)
|
dbg_imatchA1 = `TRUE;
|
dbg_imatchA1 = `TRUE;
|
| Line 5205... |
Line 5637... |
dbg_imatchA3 = `TRUE;
|
dbg_imatchA3 = `TRUE;
|
if (dbg_imatchA0|dbg_imatchA1|dbg_imatchA2|dbg_imatchA3)
|
if (dbg_imatchA0|dbg_imatchA1|dbg_imatchA2|dbg_imatchA3)
|
dbg_imatchA = `TRUE;
|
dbg_imatchA = `TRUE;
|
if (dbg_imatchA)
|
if (dbg_imatchA)
|
set_exception(tail,8'd243); // Debug exception
|
set_exception(tail,8'd243); // Debug exception
|
else begin
|
|
`endif
|
`endif
|
|
if (!exception_set) begin
|
interrupt_pc =
|
interrupt_pc =
|
// If the previous instruction was an interrupt, then inherit the address
|
// If the previous instruction was an interrupt, then inherit the address
|
(iqentry_op[(tail-3'd1)&7]==`INT && iqentry_v[(tail-3'd1)&7]==`VAL && iqentry_tgt[(tail-3'd1)&7][3:0]==4'hE) ?
|
(iqentry_op[(tail-3'd1)&7]==`INT && iqentry_v[(tail-3'd1)&7]==`VAL && iqentry_tgt[(tail-3'd1)&7][3:0]==4'hE) ?
|
(string_pc != 0 ? string_pc : iqentry_pc[(tail-3'd1)&7]) :
|
(string_pc != 0 ? string_pc : iqentry_pc[(tail-3'd1)&7]) :
|
// Otherwise inherit the address of any preceding immediate prefix.
|
// Otherwise inherit the address of any preceding immediate prefix.
|
| Line 5233... |
Line 5665... |
iqentry_mem [tail] <= fetchbuf0_mem;
|
iqentry_mem [tail] <= fetchbuf0_mem;
|
iqentry_jmp [tail] <= fetchbuf0_jmp;
|
iqentry_jmp [tail] <= fetchbuf0_jmp;
|
iqentry_fp [tail] <= fetchbuf0_fp;
|
iqentry_fp [tail] <= fetchbuf0_fp;
|
iqentry_rfw [tail] <= fetchbuf0_rfw;
|
iqentry_rfw [tail] <= fetchbuf0_rfw;
|
iqentry_tgt [tail] <= Rt0;
|
iqentry_tgt [tail] <= Rt0;
|
|
iqentry_preg [tail] <= Pn0;
|
iqentry_pred [tail] <= pregs[Pn0];
|
iqentry_pred [tail] <= pregs[Pn0];
|
// Look at the previous queue slot to see if an immediate prefix is enqueued
|
// Look at the previous queue slot to see if an immediate prefix is enqueued
|
iqentry_a0[tail] <= opcode0==`INT ? fnImm(fetchbuf0_instr) :
|
iqentry_a0[tail] <= opcode0==`INT ? fnImm(fetchbuf0_instr) :
|
fnIsBranch(opcode0) ? {{DBW-12{fetchbuf0_instr[11]}},fetchbuf0_instr[11:8],fetchbuf0_instr[23:16]} :
|
fnIsBranch(opcode0) ? {{DBW-12{fetchbuf0_instr[11]}},fetchbuf0_instr[11:8],fetchbuf0_instr[23:16]} :
|
iqentry_op[(tail-3'd1)&7]==`IMM && iqentry_v[tail-3'd1] ? {iqentry_a0[(tail-3'd1)&7][DBW-1:8],fnImm8(fetchbuf0_instr)}:
|
iqentry_op[(tail-3'd1)&7]==`IMM && iqentry_v[tail-3'd1] ? {iqentry_a0[(tail-3'd1)&7][DBW-1:8],fnImm8(fetchbuf0_instr)}:
|
| Line 5259... |
Line 5692... |
iqentry_a2_s [tail] <= rf_source[Rb0];
|
iqentry_a2_s [tail] <= rf_source[Rb0];
|
iqentry_a3_s [tail] <= rf_source[Rc0];
|
iqentry_a3_s [tail] <= rf_source[Rc0];
|
iqentry_T_s [tail] <= rf_source[Rt0];
|
iqentry_T_s [tail] <= rf_source[Rt0];
|
// Always do this because it's the first queue slot.
|
// Always do this because it's the first queue slot.
|
validate_args10(tail);
|
validate_args10(tail);
|
`ifdef DEBUG_LOGIC
|
|
end
|
|
`endif
|
|
end
|
end
|
tail0 <= tail0 + inc;
|
tail0 <= tail0 + inc;
|
tail1 <= tail1 + inc;
|
tail1 <= tail1 + inc;
|
tail2 <= tail2 + inc;
|
tail2 <= tail2 + inc;
|
queued1 = `TRUE;
|
queued1 = `TRUE;
|
| Line 5367... |
Line 5797... |
input [2:0] tail;
|
input [2:0] tail;
|
input [2:0] inc;
|
input [2:0] inc;
|
input validate_args;
|
input validate_args;
|
input unlink;
|
input unlink;
|
begin
|
begin
|
|
`ifdef SEGMENTATION
|
if (fetchbuf1_pc >= {sregs_lmt[7],12'h000} && fetchbuf1_pc[ABW-1:ABW-4]!=4'hF)
|
if (fetchbuf1_pc >= {sregs_lmt[7],12'h000} && fetchbuf1_pc[ABW-1:ABW-4]!=4'hF)
|
set_exception(tail,8'd244);
|
set_exception(tail,8'd244);
|
else begin
|
`endif
|
|
if (fnIsKMOnlyReg(Rt1) && !km && !(opcode1==`SYS || opcode1==`INT))
|
|
set_exception(tail,8'd245);
|
|
`ifdef TRAP_ILLEGALOPS
|
|
if (fnIsIllegal(opcode1,opcode1==`MLO ? rfoc1[5:0] : fnFunc(fetchbuf1_instr)))
|
|
set_exception(tail,8'd250);
|
|
`endif
|
`ifdef DEBUG_LOGIC
|
`ifdef DEBUG_LOGIC
|
if (dbg_ctrl[0] && dbg_ctrl[17:16]==2'b00 && fetchbuf1_pc==dbg_adr0)
|
if (dbg_ctrl[0] && dbg_ctrl[17:16]==2'b00 && fetchbuf1_pc==dbg_adr0)
|
dbg_imatchB0 = `TRUE;
|
dbg_imatchB0 = `TRUE;
|
if (dbg_ctrl[1] && dbg_ctrl[21:20]==2'b00 && fetchbuf1_pc==dbg_adr1)
|
if (dbg_ctrl[1] && dbg_ctrl[21:20]==2'b00 && fetchbuf1_pc==dbg_adr1)
|
dbg_imatchB1 = `TRUE;
|
dbg_imatchB1 = `TRUE;
|
| Line 5383... |
Line 5820... |
dbg_imatchB3 = `TRUE;
|
dbg_imatchB3 = `TRUE;
|
if (dbg_imatchB0|dbg_imatchB1|dbg_imatchB2|dbg_imatchB3)
|
if (dbg_imatchB0|dbg_imatchB1|dbg_imatchB2|dbg_imatchB3)
|
dbg_imatchB = `TRUE;
|
dbg_imatchB = `TRUE;
|
if (dbg_imatchB)
|
if (dbg_imatchB)
|
set_exception(tail,8'd243); // debug excpetion
|
set_exception(tail,8'd243); // debug excpetion
|
else begin
|
|
`endif
|
`endif
|
|
if (!exception_set) begin
|
// If an instruction wasn't enqueued or it wasn't an interrupt instruction then
|
// If an instruction wasn't enqueued or it wasn't an interrupt instruction then
|
// the interrupt pc will need to be set. Othersise this enqueue will inherit
|
// the interrupt pc will need to be set. Othersise this enqueue will inherit
|
// from the previous one.
|
// from the previous one.
|
if (!queued1 || !(opcode0==`INT && Rt0[3:0]==4'hE))
|
if (!queued1 || !(opcode0==`INT && Rt0[3:0]==4'hE))
|
interrupt_pc = (iqentry_op[(tail-3'd1)&7]==`INT && iqentry_v[(tail-3'd1)&7]==`VAL && iqentry_tgt[(tail-3'd1)&7][3:0]==4'hE) ?
|
interrupt_pc = (iqentry_op[(tail-3'd1)&7]==`INT && iqentry_v[(tail-3'd1)&7]==`VAL && iqentry_tgt[(tail-3'd1)&7][3:0]==4'hE) ?
|
| Line 5416... |
Line 5853... |
iqentry_mem [tail] <= fetchbuf1_mem;
|
iqentry_mem [tail] <= fetchbuf1_mem;
|
iqentry_jmp [tail] <= fetchbuf1_jmp;
|
iqentry_jmp [tail] <= fetchbuf1_jmp;
|
iqentry_fp [tail] <= fetchbuf1_fp;
|
iqentry_fp [tail] <= fetchbuf1_fp;
|
iqentry_rfw [tail] <= fetchbuf1_rfw;
|
iqentry_rfw [tail] <= fetchbuf1_rfw;
|
iqentry_tgt [tail] <= Rt1;
|
iqentry_tgt [tail] <= Rt1;
|
|
iqentry_preg [tail] <= Pn1;
|
iqentry_pred [tail] <= pregs[Pn1];
|
iqentry_pred [tail] <= pregs[Pn1];
|
// Look at the previous queue slot to see if an immediate prefix is enqueued
|
// Look at the previous queue slot to see if an immediate prefix is enqueued
|
// But don't allow it for a branch
|
// But don't allow it for a branch
|
iqentry_a0[tail] <= opcode1==`INT ? fnImm(fetchbuf1_instr) :
|
iqentry_a0[tail] <= opcode1==`INT ? fnImm(fetchbuf1_instr) :
|
fnIsBranch(opcode1) ? {{DBW-12{fetchbuf1_instr[11]}},fetchbuf1_instr[11:8],fetchbuf1_instr[23:16]} :
|
fnIsBranch(opcode1) ? {{DBW-12{fetchbuf1_instr[11]}},fetchbuf1_instr[11:8],fetchbuf1_instr[23:16]} :
|
| Line 5444... |
Line 5882... |
iqentry_a2_s [tail] <= rf_source[Rb1];
|
iqentry_a2_s [tail] <= rf_source[Rb1];
|
iqentry_a3_s [tail] <= rf_source[Rc1];
|
iqentry_a3_s [tail] <= rf_source[Rc1];
|
iqentry_T_s [tail] <= rf_source[Rt1];
|
iqentry_T_s [tail] <= rf_source[Rt1];
|
if (validate_args)
|
if (validate_args)
|
validate_args11(tail);
|
validate_args11(tail);
|
`ifdef DEBUG_LOGIC
|
|
end
|
|
`endif
|
|
end
|
end
|
tail0 <= tail0 + inc;
|
tail0 <= tail0 + inc;
|
tail1 <= tail1 + inc;
|
tail1 <= tail1 + inc;
|
tail2 <= tail2 + inc;
|
tail2 <= tail2 + inc;
|
end
|
end
|
| Line 5507... |
Line 5942... |
iqentry_a2_v [tail] <= fnSource2_v( opcode0, fnFunc(fetchbuf0_instr)) | rf_v[Rb0];
|
iqentry_a2_v [tail] <= fnSource2_v( opcode0, fnFunc(fetchbuf0_instr)) | rf_v[Rb0];
|
iqentry_a3_v [tail] <= fnSource3_v( opcode0 ) | rf_v[ Rc0 ];
|
iqentry_a3_v [tail] <= fnSource3_v( opcode0 ) | rf_v[ Rc0 ];
|
iqentry_T_v [tail] <= fnSourceT_v( opcode0 ) | rf_v[ Rt0 ];
|
iqentry_T_v [tail] <= fnSourceT_v( opcode0 ) | rf_v[ Rt0 ];
|
if (fetchbuf0_rfw|fetchbuf0_pfw) begin
|
if (fetchbuf0_rfw|fetchbuf0_pfw) begin
|
$display("regv[%d] = %d", Rt0,rf_v[ Rt0 ]);
|
$display("regv[%d] = %d", Rt0,rf_v[ Rt0 ]);
|
rf_v[ Rt0 ] = Rt0==7'd0;
|
rf_v[ Rt0 ] = fnRegIsAutoValid(Rt0);
|
$display("reg[%d] <= INV",Rt0);
|
$display("reg[%d] <= INV",Rt0);
|
rf_source[ Rt0 ] <= { fetchbuf0_mem, tail }; // top bit indicates ALU/MEM bus
|
rf_source[ Rt0 ] <= { fetchbuf0_mem, tail }; // top bit indicates ALU/MEM bus
|
$display("10:rf_src[%d] <= %d, insn=%h", Rt0, tail,fetchbuf0_instr);
|
$display("10:rf_src[%d] <= %d, insn=%h", Rt0, tail,fetchbuf0_instr);
|
|
invalidate_pregs(tail, Rt0, fetchbuf0_mem);
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
task validate_args11;
|
task validate_args11;
|
| Line 5526... |
Line 5962... |
iqentry_a2_v [tail] <= fnSource2_v( opcode1, fnFunc(fetchbuf1_instr) ) | rf_v[ Rb1 ];
|
iqentry_a2_v [tail] <= fnSource2_v( opcode1, fnFunc(fetchbuf1_instr) ) | rf_v[ Rb1 ];
|
iqentry_a3_v [tail] <= fnSource3_v( opcode1 ) | rf_v[ Rc1 ];
|
iqentry_a3_v [tail] <= fnSource3_v( opcode1 ) | rf_v[ Rc1 ];
|
iqentry_T_v [tail] <= fnSourceT_v( opcode1 ) | rf_v[ Rt1 ];
|
iqentry_T_v [tail] <= fnSourceT_v( opcode1 ) | rf_v[ Rt1 ];
|
if (fetchbuf1_rfw|fetchbuf1_pfw) begin
|
if (fetchbuf1_rfw|fetchbuf1_pfw) begin
|
$display("1:regv[%d] = %d", Rt1,rf_v[ Rt1 ]);
|
$display("1:regv[%d] = %d", Rt1,rf_v[ Rt1 ]);
|
rf_v[ Rt1 ] = Rt1==7'd0;
|
rf_v[ Rt1 ] = fnRegIsAutoValid(Rt1);
|
$display("reg[%d] <= INV",Rt1);
|
$display("reg[%d] <= INV",Rt1);
|
rf_source[ Rt1 ] <= { fetchbuf1_mem, tail }; // top bit indicates ALU/MEM bus
|
rf_source[ Rt1 ] <= { fetchbuf1_mem, tail }; // top bit indicates ALU/MEM bus
|
|
invalidate_pregs(tail, Rt1, fetchbuf1_mem);
|
$display("11:rf_src[%d] <= %d, insn=%h", Rt1, tail,fetchbuf0_instr);
|
$display("11:rf_src[%d] <= %d, insn=%h", Rt1, tail,fetchbuf0_instr);
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
| Line 5572... |
Line 6009... |
|
|
if (!fetchbuf0_pfw) begin
|
if (!fetchbuf0_pfw) begin
|
iqentry_p_v [tail1] <= rf_v [{1'b1,2'h0,Pn1}] || cond1 < 4'h2;
|
iqentry_p_v [tail1] <= rf_v [{1'b1,2'h0,Pn1}] || cond1 < 4'h2;
|
iqentry_p_s [tail1] <= rf_source [{1'b1,2'h0,Pn1}];
|
iqentry_p_s [tail1] <= rf_source [{1'b1,2'h0,Pn1}];
|
end
|
end
|
else if ((Rt0 != 7'd0 && Pn1==Rt0[3:0]) && (Rt0 & 7'h70)==7'h40) begin
|
else if ((Rt0 != 7'd0 && (Pn1==Rt0[3:0] || Rt0==7'h70)) && ((Rt0 & 7'h70)==7'h40)||Rt0==7'h70) begin
|
iqentry_p_v [tail1] <= cond1 < 4'h2;
|
iqentry_p_v [tail1] <= cond1 < 4'h2;
|
iqentry_p_s [tail1] <= {fetchbuf0_mem, tail0};
|
iqentry_p_s [tail1] <= {fetchbuf0_mem, tail0};
|
end
|
end
|
else begin
|
else begin
|
iqentry_p_v [tail1] <= rf_v[{1'b1,2'h0,Pn1}] || cond1 < 4'h2;
|
iqentry_p_v [tail1] <= rf_v[{1'b1,2'h0,Pn1}] || cond1 < 4'h2;
|
| Line 5664... |
Line 6101... |
end
|
end
|
end
|
end
|
if (queued1|queued2) begin
|
if (queued1|queued2) begin
|
if (fetchbuf0_rfw|fetchbuf0_pfw) begin
|
if (fetchbuf0_rfw|fetchbuf0_pfw) begin
|
$display("regv[%d] = %d", Rt0,rf_v[ Rt0 ]);
|
$display("regv[%d] = %d", Rt0,rf_v[ Rt0 ]);
|
rf_v[ Rt0 ] = Rt0==7'd0;
|
rf_v[ Rt0 ] = fnRegIsAutoValid(Rt0);
|
$display("reg[%d] <= INV",Rt0);
|
$display("reg[%d] <= INV",Rt0);
|
rf_source[ Rt0 ] <= { fetchbuf0_mem, tail0 }; // top bit indicates ALU/MEM bus
|
rf_source[ Rt0 ] <= { fetchbuf0_mem, tail0 }; // top bit indicates ALU/MEM bus
|
$display("12:rf_src[%d] <= %d, insn=%h", Rt0, tail0,fetchbuf0_instr);
|
$display("12:rf_src[%d] <= %d, insn=%h", Rt0, tail0,fetchbuf0_instr);
|
|
invalidate_pregs(tail0, Rt0, fetchbuf0_mem);
|
end
|
end
|
end
|
end
|
if (queued2) begin
|
if (queued2) begin
|
if (fetchbuf1_rfw|fetchbuf1_pfw) begin
|
if (fetchbuf1_rfw|fetchbuf1_pfw) begin
|
$display("1:regv[%d] = %d", Rt1,rf_v[ Rt1 ]);
|
$display("1:regv[%d] = %d", Rt1,rf_v[ Rt1 ]);
|
rf_v[ Rt1 ] = Rt1==7'd0;
|
rf_v[ Rt1 ] = fnRegIsAutoValid(Rt1);
|
$display("reg[%d] <= INV",Rt1);
|
$display("reg[%d] <= INV",Rt1);
|
rf_source[ Rt1 ] <= { fetchbuf1_mem, tail1 }; // top bit indicates ALU/MEM bus
|
rf_source[ Rt1 ] <= { fetchbuf1_mem, tail1 }; // top bit indicates ALU/MEM bus
|
|
invalidate_pregs(tail1, Rt1, fetchbuf1_mem);
|
end
|
end
|
end
|
end
|
end
|
end
|
endtask
|
endtask
|
|
|
| Line 5796... |
Line 6235... |
iqentry_a3_v [id[2:0]] <= `TRUE;
|
iqentry_a3_v [id[2:0]] <= `TRUE;
|
iqentry_T_v [id[2:0]] <= `TRUE;
|
iqentry_T_v [id[2:0]] <= `TRUE;
|
iqentry_out [id[2:0]] <= `FALSE;
|
iqentry_out [id[2:0]] <= `FALSE;
|
iqentry_agen [id[2:0]] <= `FALSE;
|
iqentry_agen [id[2:0]] <= `FALSE;
|
iqentry_tgt[id[2:0]] <= {1'b1,2'h1,(exc==8'd243)?4'hB:4'hD}; // Target EPC
|
iqentry_tgt[id[2:0]] <= {1'b1,2'h1,(exc==8'd243)?4'hB:4'hD}; // Target EPC
|
|
exception_set = `TRUE;
|
|
end
|
|
endtask
|
|
|
|
// The core should really invalidate all the predicate registers when the
|
|
// sideways slice of all the pregs is manipulated. But then the problem is
|
|
// reading the result register into all the predicate registers at once.
|
|
// The source for each register would be a bit field of the result register
|
|
// and the core does not support this sort of thing.
|
|
// So. After manipulating the sideways slice of predicate registers the
|
|
// instruction should be followed with a SYNC instruction to ensure that
|
|
// the results are picked up.
|
|
// To be fixed one day.
|
|
task invalidate_pregs;
|
|
input [2:0] tail;
|
|
input [6:0] Rt;
|
|
input mem;
|
|
begin
|
|
if (Rt==7'h70) begin
|
|
rf_v[7'h40] <= `INV;
|
|
rf_v[7'h41] <= `INV;
|
|
rf_v[7'h42] <= `INV;
|
|
rf_v[7'h43] <= `INV;
|
|
rf_v[7'h44] <= `INV;
|
|
rf_v[7'h45] <= `INV;
|
|
rf_v[7'h46] <= `INV;
|
|
rf_v[7'h47] <= `INV;
|
|
rf_v[7'h48] <= `INV;
|
|
rf_v[7'h49] <= `INV;
|
|
rf_v[7'h4A] <= `INV;
|
|
rf_v[7'h4B] <= `INV;
|
|
rf_v[7'h4C] <= `INV;
|
|
rf_v[7'h4D] <= `INV;
|
|
rf_v[7'h4E] <= `INV;
|
|
rf_v[7'h4F] <= `INV;
|
|
rf_source[7'h40] <= { mem, tail };
|
|
rf_source[7'h41] <= { mem, tail };
|
|
rf_source[7'h42] <= { mem, tail };
|
|
rf_source[7'h43] <= { mem, tail };
|
|
rf_source[7'h44] <= { mem, tail };
|
|
rf_source[7'h45] <= { mem, tail };
|
|
rf_source[7'h46] <= { mem, tail };
|
|
rf_source[7'h47] <= { mem, tail };
|
|
rf_source[7'h48] <= { mem, tail };
|
|
rf_source[7'h49] <= { mem, tail };
|
|
rf_source[7'h4A] <= { mem, tail };
|
|
rf_source[7'h4B] <= { mem, tail };
|
|
rf_source[7'h4C] <= { mem, tail };
|
|
rf_source[7'h4D] <= { mem, tail };
|
|
rf_source[7'h4E] <= { mem, tail };
|
|
rf_source[7'h4F] <= { mem, tail };
|
|
end
|
end
|
end
|
endtask
|
endtask
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|
|
endmodule
|
endmodule
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