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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_BranchHistory.v] - Diff between revs 3 and 9

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//=============================================================================
//=============================================================================
//        __
//        __
//   \\__/ o\    (C) 2013  Robert Finch, Stratford
//   \\__/ o\    (C) 2013,2015  Robert Finch, Stratford
//    \  __ /    All rights reserved.
//    \  __ /    All rights reserved.
//     \/_//     robfinch<remove>@finitron.ca
//     \/_//     robfinch<remove>@finitron.ca
//       ||
//       ||
//  
//  
//      Thor_BranchHistory.v
//      Thor_BranchHistory.v
Line 39... Line 39...
reg [2:0] gbl_branch_hist;
reg [2:0] gbl_branch_hist;
reg [1:0] branch_history_table [255:0];
reg [1:0] branch_history_table [255:0];
// For simulation only, initialize the history table to zeros.
// For simulation only, initialize the history table to zeros.
// In the real world we don't care.
// In the real world we don't care.
initial begin
initial begin
 
    gbl_branch_hist = 0;
        for (n = 0; n < 256; n = n + 1)
        for (n = 0; n < 256; n = n + 1)
                branch_history_table[n] = 0;
                branch_history_table[n] = 0;
end
end
wire [7:0] bht_wa = {xpc[7:2],gbl_branch_hist[2:1]};             // write address
wire [7:0] bht_wa = {xpc[7:2],gbl_branch_hist[2:1]};             // write address
wire [7:0] bht_ra = {pc[7:2],gbl_branch_hist[2:1]};      // read address (IF stage)
wire [7:0] bht_ra = {pc[7:2],gbl_branch_hist[2:1]};      // read address (IF stage)

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