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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_BranchHistory.v] - Diff between revs 3 and 9
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| Rev 3 |
Rev 9 |
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//=============================================================================
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//=============================================================================
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// __
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// __
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// \\__/ o\ (C) 2013 Robert Finch, Stratford
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// \\__/ o\ (C) 2013,2015 Robert Finch, Stratford
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// Thor_BranchHistory.v
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// Thor_BranchHistory.v
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reg [2:0] gbl_branch_hist;
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reg [2:0] gbl_branch_hist;
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reg [1:0] branch_history_table [255:0];
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reg [1:0] branch_history_table [255:0];
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// For simulation only, initialize the history table to zeros.
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// For simulation only, initialize the history table to zeros.
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// In the real world we don't care.
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// In the real world we don't care.
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initial begin
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initial begin
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gbl_branch_hist = 0;
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for (n = 0; n < 256; n = n + 1)
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for (n = 0; n < 256; n = n + 1)
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branch_history_table[n] = 0;
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branch_history_table[n] = 0;
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end
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end
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wire [7:0] bht_wa = {xpc[7:2],gbl_branch_hist[2:1]}; // write address
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wire [7:0] bht_wa = {xpc[7:2],gbl_branch_hist[2:1]}; // write address
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wire [7:0] bht_ra = {pc[7:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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wire [7:0] bht_ra = {pc[7:2],gbl_branch_hist[2:1]}; // read address (IF stage)
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