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https://opencores.org/ocsvn/thor/thor/trunk
[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_TLB.v] - Diff between revs 3 and 10
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| Rev 3 |
Rev 10 |
| Line 156... |
Line 156... |
end
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end
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`TLBDMissAdr: dmiss_addr <= dati;
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`TLBDMissAdr: dmiss_addr <= dati;
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`TLBIMissAdr: imiss_addr <= dati;
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`TLBIMissAdr: imiss_addr <= dati;
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`TLBPageTblAddr: PageTblAddr <= dati;
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`TLBPageTblAddr: PageTblAddr <= dati;
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`TLBPageTblCtrl: PageTblCtrl <= dati;
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`TLBPageTblCtrl: PageTblCtrl <= dati;
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default: ;
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endcase
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endcase
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end
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end
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`TLB_EN:
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`TLB_EN:
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TLBenabled <= 1'b1;
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TLBenabled <= 1'b1;
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`TLB_DIS:
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`TLB_DIS:
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TLBenabled <= 1'b0;
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TLBenabled <= 1'b0;
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`TLB_INVALL:
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`TLB_INVALL:
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TLBValid <= 64'd0;
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TLBValid <= 64'd0;
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default: ;
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endcase
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endcase
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end
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end
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else if (state==3'd2) begin
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else if (state==3'd2) begin
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case(op)
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case(op)
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`TLB_P:
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`TLB_P:
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| Line 266... |
Line 268... |
default: ppc[DBW-1:12] = pc[DBW-1:12];
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default: ppc[DBW-1:12] = pc[DBW-1:12];
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endcase
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endcase
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end
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end
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wire [DBW-1:0] eas = ea[DBW-1:12] >> {PageSize,1'b0};
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wire [DBW-1:0] eas = ea[DBW-1:12] >> {PageSize,1'b0};
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always @(ea)
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always @(eas or ASID or q or TLBG or TLBValid)
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for (n = 0; n < 8; n = n + 1)
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for (n = 0; n < 8; n = n + 1)
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DMatch[n[2:0]] = (eas[DBW-1:3]==TLBVirtPage[{n,eas[2:0]}]) &&
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DMatch[n[2:0]] = (eas[DBW-1:3]==TLBVirtPage[{n,eas[2:0]}]) &&
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((TLBASID[{n,eas[2:0]}]==ASID) || TLBG[{n,eas[2:0]}]) &&
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((TLBASID[{n,eas[2:0]}]==ASID) || TLBG[{n,eas[2:0]}]) &&
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TLBValid[{q[2:0],eas[2:0]}];
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TLBValid[{q[2:0],eas[2:0]}];
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always @(DMatch)
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always @(DMatch)
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