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[/] [thor/] [trunk/] [rtl/] [verilog/] [Thor_TLB.v] - Diff between revs 3 and 10

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Rev 3 Rev 10
Line 156... Line 156...
                                                end
                                                end
                        `TLBDMissAdr:   dmiss_addr <= dati;
                        `TLBDMissAdr:   dmiss_addr <= dati;
                        `TLBIMissAdr:   imiss_addr <= dati;
                        `TLBIMissAdr:   imiss_addr <= dati;
                        `TLBPageTblAddr:        PageTblAddr <= dati;
                        `TLBPageTblAddr:        PageTblAddr <= dati;
                        `TLBPageTblCtrl:        PageTblCtrl <= dati;
                        `TLBPageTblCtrl:        PageTblCtrl <= dati;
 
                        default: ;
                        endcase
                        endcase
                        end
                        end
                `TLB_EN:
                `TLB_EN:
                        TLBenabled <= 1'b1;
                        TLBenabled <= 1'b1;
                `TLB_DIS:
                `TLB_DIS:
                        TLBenabled <= 1'b0;
                        TLBenabled <= 1'b0;
                `TLB_INVALL:
                `TLB_INVALL:
                        TLBValid <= 64'd0;
                        TLBValid <= 64'd0;
 
                default:  ;
                endcase
                endcase
        end
        end
        else if (state==3'd2) begin
        else if (state==3'd2) begin
                case(op)
                case(op)
                `TLB_P:
                `TLB_P:
Line 266... Line 268...
        default:        ppc[DBW-1:12] = pc[DBW-1:12];
        default:        ppc[DBW-1:12] = pc[DBW-1:12];
        endcase
        endcase
end
end
 
 
wire [DBW-1:0] eas = ea[DBW-1:12] >> {PageSize,1'b0};
wire [DBW-1:0] eas = ea[DBW-1:12] >> {PageSize,1'b0};
always @(ea)
always @(eas or ASID or q or TLBG or TLBValid)
for (n = 0; n < 8; n = n + 1)
for (n = 0; n < 8; n = n + 1)
        DMatch[n[2:0]] = (eas[DBW-1:3]==TLBVirtPage[{n,eas[2:0]}]) &&
        DMatch[n[2:0]] = (eas[DBW-1:3]==TLBVirtPage[{n,eas[2:0]}]) &&
                                ((TLBASID[{n,eas[2:0]}]==ASID) || TLBG[{n,eas[2:0]}]) &&
                                ((TLBASID[{n,eas[2:0]}]==ASID) || TLBG[{n,eas[2:0]}]) &&
                                TLBValid[{q[2:0],eas[2:0]}];
                                TLBValid[{q[2:0],eas[2:0]}];
always @(DMatch)
always @(DMatch)

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